MAX5866 19-3223 Rev 0 2/04 Ultra-Low-Power, High-Dynamic- Performance, 60Msps Analog Front End General Description Features The MAX5866 ultra-low-power, highly integrated analog Integrated Dual, 8-Bit ADCs and Dual, 10-Bit DACs front end is ideal for portable communication equipment Ultra-Low Power such as handsets, PDAs, WLAN, and 3G wireless termi- 80mW at f = 60MHz (R Mode) nals. The MAX5866 integrates dual, 8-bit receive ADCs CLK x and dual, 10-bit transmit DACs while providing the high- 52.5mW at f = 60MHz (T Mode) CLK x est dynamic performance at ultra-low power. The ADCs Low-Current Idle and Shutdown Modes analog I-Q input amplifiers are fully differential and Excellent Dynamic Performance accept 1V full-scale signals. Typical I-Q channel P-P 48dB SINAD at f = 25MHz (ADC) IN phase matching is 0.2 and amplitude matching is 64.2dBc SFDR at f = 6MHz (DAC) OUT 0.05dB. The ADCs feature 48dB SINAD and 70.1dBc spurious-free dynamic range (SFDR) at f = 25MHz and IN Excellent Gain/Phase Match f = 60MHz. The DACs analog I-Q outputs are fully CLK 0.2 Phase, 0.05dB Gain at f = 25MHz (ADC) IN differential with 400mV full-scale output, and 1.4V com- Internal/External Reference Option mon-mode level. Typical I-Q channel phase matching is 0.4 and gain matching is 0.1dB. The DACs also fea- +2.7V to +3.3V Digital Output Level (TTL/CMOS ture dual, 10-bit resolution with 64.2dBc SFDR, at f = OUT Compatible) 6MHz and f = 60MHz. CLK Multiplexed Parallel Digital Input/Output for The ADCs and DACs operate simultaneously or indepen- ADCs/DACs dently for frequency-division duplex (FDD) and time-divi- sion duplex (TDD) modes. A 3-wire serial interface Miniature 48-Pin Thin QFN Package (7mm 7mm) controls power-down and transceiver modes of opera- Evaluation Kit Available (Order MAX5865EVKIT) tion. The typical operating power is 96mW at f = CLK 60MHz with the ADCs and DACs operating simultane- Ordering Information ously in transceiver mode. The MAX5866 features an internal 1.024V voltage reference that is stable over the PART TEMP RANGE PIN-PACKAGE entire operating power-supply range and temperature 48 Thin QFN-EP* range. The MAX5866 operates on a +2.7V to +3.3V ana- MAX5866ETM -40C to +85C (7mm x 7mm) log power supply and a +2.7V to +3.3V digital I/O power supply for logic compatibility. The quiescent current is *EP = Exposed paddle. 12mA in idle mode and 1A in shutdown mode. The Functional Diagram MAX5866 is specified for the extended (-40C to +85C) temperature range and is available in a 48-pin thin QFN package. MAX5866 Applications IA+ ADC ADC IA- Narrowband/Wideband CDMA Handsets OUTPUT DA0DA7 and PDAs QA+ MUX ADC QA- Fixed/Mobile Broadband Wireless Modems CLK 3G Wireless Terminals ID+ DAC DAC VSAT Modems ID- INPUT DD0DD9 QD+ MUX DAC QD- REFP COM REFN SERIAL DIN REF INTERFACE SCLK REFIN AND AND SYSTEM CS CONTROL BIAS Pin Configuration appears at end of data sheet. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com. EVALUATION KIT AVAILABLEUltra-Low-Power, High-Dynamic- Performance, 60Msps Analog Front End ABSOLUTE MAXIMUM RATINGS V to GND, OV to OGND................................-0.3V to +3.4V Continuous Power Dissipation (T = +70C) DD DD A GND to OGND.......................................................-0.3V to +0.3V 48-Pin Thin QFN (derate 26.3mW/C above IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN, +70C)..............................................................................2.1W REFIN, COM to GND..............................-0.3V to (V + 0.3V) Thermal Resistance .................................................+38C/W DD JA DD0DD9, SCLK, DIN, CS, CLK, Operating Temperature Range ...........................-40C to +85C DA0DA7 to OGND .............................-0.3V to (OV + 0.3V) Junction Temperature......................................................+150C DD Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V = 3V, OV = 3.0V, internal reference (1.024V), C 10pF on all digital outputs, f = 60MHz, 50% duty cycle, ADC input ampli- DD DD L CLK tude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C = C = C = 0.33F, REFP REFN COM Xcvr mode, unless otherwise noted. Typical values are at T = +25C, unless otherwise noted.) (Note 1) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Analog Supply Voltage V 2.7 3.0 3.3 V DD Output Supply Voltage OV 2.7 V V DD DD ADC oper at ing m ode, f = 25MH z, f = IN C LK 32 38 60M H z, DAC op er ating m ode, f = 6MH z OUT ADC operating mode (Rx), f = 25MHz, IN f = 60MH z, DAC digital inputs at zero or CLK 26.6 OV D D mA DAC operating mode (Tx), f = 6MHz, OUT 17.5 f = 60MH z, ADC off V Supply Current CLK DD Standby mode, DAC digital inputs and CLK 2.0 at zero or OV DD Idle mode, DAC digital inputs at zero or 14.5 OV , f = 60M H z DD CLK Shutdown mode, digital inputs and CLK at 1A zero or OV , CS = OV DD DD ADC operating mode, f = 25MHz, f = IN CLK 9.9 mA 60MHz, DAC operating mode, f = 6MHz OUT Idle mode, DAC digital inputs at zero or OV Supply Current 108.4 DD OV f = 60M H z DD, CLK A Shutdown mode, DAC digital inputs and 1 CLK at zero or OV , CS = OV DD DD 2 MAX5866