Quad Low Offset, Low Power Operational Amplifier Data Sheet OP400 FEATURES FUNCTIONAL BLOCK DIAGRAMS Low input offset voltage: 150 V (maximum) OUTA 1 16 OUT D Low offset voltage drift over 55C to +125C: 1.2 V/C IN A 2 15 IN D OUT A 1 14 OUT D + (maximum) +IN A 3 14 +IN D IN A 2 13 IN D + +IN A 3 12 +IN D V+ 4 13 V Low supply current (per amplifier): 725 A (maximum) OP400 +IN B 5 12 +IN C V+ 4 11 V OP400 High open-loop gain: 5000 V/mV (minimum) + IN B 6 11 IN C +IN B 5 10 +IN C Input bias current: 3 nA (maximum) + IN B 6 9 IN C OUT B 7 10 OUT C Low noise voltage density: 11 nV/Hz at 1 kHz NC 8 9 NC OUT B 7 8 OUT C Stable with large capacitive loads: 10 nF typical NC = NO CONNECT Available in die form Figure 1. 14-Lead Ceramic Dual In-Line Figure 2. 16-Lead Standard Small Package CERDIP and 14-Lead Plastic Outline Package SOIC W Dual In-Line Package PDIP nulling. The OP400 conforms to the industry-standard quad GENERAL DESCRIPTION pinout, which does not have null terminals. The OP400 is the first monolithic quad operational amplifier The OP400 features low power consumption, drawing less than that features OP77-type performance. Precision performance is 725 A per amplifier. The total current drawn by this quad not sacrificed with the OP400 to obtain the space and cost savings offered by quad amplifiers. amplifier is less than that of a single OP07, yet the OP400 offers significant improvements over this industry-standard op amp. The OP400 features an extremely low input offset voltage of less Voltage noise density of the OP400 is a low 11 nV/Hz at 10 Hz, than 150 V with a drift of less than 1.2 V/C, guaranteed over half that of most competitive devices. the full military temperature range. Open-loop gain of the OP400 The OP400 is an ideal choice for applications requiring multiple is more than 5 million into a 10 k load, input bias current is precision operational amplifiers and where low power less than 3 nA, common-mode rejection (CMR) is more than consumption is critical. 120 dB, and power supply rejection ratio (PSRR) is less than 1.8 V/V. On-chip Zener zap trimming achieves the low input offset voltage of the OP400 and eliminates the need for offset V+ BIAS VOLTAGE OUT LIMITING NETWORK +IN IN V Figure 3. Simplified Schematic (One of Four Amplifiers Is Shown) Rev. I Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 00304-001 00304-003 00304-002 + + + +OP400 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................6 Functional Block Diagrams ............................................................. 1 Applications Information .............................................................. 11 General Description ......................................................................... 1 Dual Low Power Instrumentation Amplifier ......................... 11 Revision History ............................................................................... 2 Bipolar Current Transmitter ..................................................... 12 Specifications ..................................................................................... 3 Differential Output Instrumentation Amplifier .................... 12 Electrical Characteristics ............................................................. 3 Multiple Output Tracking Voltage Reference ......................... 13 Absolute Maximum Ratings ............................................................ 5 Outline Dimensions ....................................................................... 14 Thermal Resistance ...................................................................... 5 Ordering Guide .......................................................................... 15 ESD Caution .................................................................................. 5 SMD Parts and Equivalents ...................................................... 15 REVISION HISTORY 5/2018Rev. H to Rev. I 6/2003Rev. B to Rev. C Changes to Figure 19 ........................................................................ 8 Edits to Specifications ....................................................................... 2 Changed Applications Section to Applications Information Section .............................................................................................. 11 10/2002Rev. A to Rev. B Changes to Ordering Guide .......................................................... 15 Addition of Absolute Maximum Ratings ....................................... 5 Edits to Outline Dimensions......................................................... 12 1/2013Rev. G to Rev. H Changes to Features Section and General Description Section ....... 1 4/2002Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 15 Edits to Features................................................................................. 1 Edits to Ordering Information ........................................................ 1 2/2011Rev. F to Rev. G Edits to Pin Connections .................................................................. 1 Added S Package to Storage Temperature Range in Table 4 ....... 5 Edits to General Descriptions ..................................................... 1, 2 Updated Outline Dimensions ....................................................... 15 Edits to Package Type ....................................................................... 2 12/2008Rev. E to Rev. F Added New Figure 28, Renumbered Sequentially ..................... 10 Updated Outline Dimensions ....................................................... 15 1/2007Rev. D to Rev. E Updated Format .................................................................. Universal Changes to Figure 1 and Figure 2 ................................................... 1 Removed Figure 4 ............................................................................. 4 Changes to Table 3 ............................................................................ 4 Changes to Figure 16 through Figure 19, Figure 21..................... 8 Changes to Figure 27 ........................................................................ 9 Changes to Figure 28 ...................................................................... 10 Changes to Figure 33 ...................................................................... 13 Updated Outline Dimensions ....................................................... 14 3/2006Rev. C to Rev. D Updated Format .................................................................. Universal Deleted Wafer Test Limits Table ..................................................... 4 New Package Drawing: R-14 ......................................................... 15 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 16 Rev. I Page 2 of 15