TISP8200M, BUFFERED P-GATE SCR DUAL TISP8201M, BUFFERED N-GATE SCR DUAL COMPLEMENTARY BUFFERED-GATE SCRS FOR DUAL POLARITY SLIC OVERVOLTAGE PROTECTION TISP8200M & TISP8201M Agency Recognition High Performance Protection for SLICs with +ve & -ve Battery Supplies Description TISP8200M, Negative Overvoltage Protector UL File Number: E215609 Wide 0 to -90 V Programming Range Low 5 mA max. Gate Triggering Current High -150 mA min. Holding Current TISP8200M D Package (Top View) G1 1 8 NC TISP8201M, Positive Overvoltage Protector Wide 0 to +90 V Programming Range 2 7 A K1 Low -5 mA max. Gate Triggering Current 20 mA min. Holding Current K2 3 6 A G2 4 5 NC Rated for International Surge Wave Shapes MDRXAKC NC - No internal connection I tsp Wave Shape Standard TISP8200M Device Symbol A K1 2/10 s Telcordia GR-1089-CORE 210 10/700 s ITU-T K.20, K.21 & K.45 70 10/1000 s Telcordia GR-1089-CORE 45 G1 A Surface Mount Small-Outline Package A G2 ................................................. UL Recognized Components Description SDRXAJB K2 The TISP8200M/TISP8201M combination has been designed to protect dual polarity supply rail monolithic SLICs (Subscriber TISP8201M D Package (Top View) Line Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. Protection G1 1 8 NC against negative overvoltages is given by the TISP8200M. 7 A1 2 K Protection against positive overvoltages is given by the TISP8201M. Both parts are in 8-pin small-outline surface mount packages. A2 3 6 K 5 G2 4 NC The TISP8200M has an array of two buffered P-gate SCRs with a MDRXALC common anode connection. Each SCR cathode and gate has a NC - No internal connection separate terminal connection. The NPN buffer transistors reduce the gate supply current. TISP8201M Device Symbol A1 In use, the cathodes of the TISP8200M SCRs are connected to the two conductors of the POTS line (see applications information). The gates are connected to the appropriate negative voltage battery G1 feed of the SLIC driving the line conductor pair. This ensures that the TISP8200M protection voltage tracks the SLIC negative supply K voltage. The anode of the TISP8200M is connected to the SLIC K common. G2 How to Order Device PackageCarrier Order As A2 SDRXAKB TISP8200M D (8-pin Small-Outline) Embossed Tape Reeled TISP8200MDR-S TISP8201M D (8-pin Small-Outline) Embossed Tape Reeled TISP8201MDR-S MAY 1998 REVISED JULY 2019 *RoHS Directive 2015/863, Mar 31, 2015 and Annex. Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. WARNING Cancer and Reproductive Harm The products described herein and this document are subject to specific legal disclaimers as set forth on the last www.P65Warnings.ca.gov page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP8200M & TISP8201M Description Negative overvoltages are initially clipped close to the SLIC negative supply by emitter follower action of the NPN buffer transistor. If sufficient clipping current flows, the SCR will regenerate and switch into a low voltage on-state condition. As the overvoltage subsides, the high holding current of the SCR helps prevent d.c. latchup. The TISP8201M has an array of two buffered N-gate SCRs with a common cathode connection. Each SCR anode and gate has a separate terminal connection. The PNP buffer transistors reduce the gate supply current. In use, the anodes of the TISP8201M SCRs are connected to the two conductors of the POTS line (see applications information). The gates are connected to the appropriate positive voltage battery feed of the SLIC driving that line pair. This ensures that the TISP8201M protection voltage tracks the SLIC positive supply voltage. The cathode of the TISP8201M is connected to the SLIC common. Positive overvoltages are initially clipped close to the SLIC positive supply by emitter follower action of the PNP buffer transistor. If sufficient clipping current flows, the SCR will regenerate and switch into a low voltage on-state condition. As the overvoltage subsides, the SLIC pulls the conductor voltage down to its normal negative value and this commutates the conducting SCR into a reverse biassed condition. Absolute Maximum Ratings for TISP8200M, T = 25 C (Unless Otherwise Noted) A Rating Symbol Value Unit Repetitive peak off-state voltage, TISP8200M V =0 V -120 V GK DRM Repetitive peak reverse voltage, V =-70V V 120 V GA RRM Non-repetitive peak on-state pulse current, (see Notes 1 and 2) 10/1000 s (Telcordia/Bellcore GR-1089-CORE, Issue 2, February 1999, Section 4) -45 I A TSP 5/310 s (ITU-T K.20, K.21& K.45, K.44 open-circuit voltage wave shape 10/700 s) -70 2/10 s (Telcordia/Bellcore GR-1089-CORE, Issue 2, February 1999, Section 4) -210 Non-repetitive peak on-state current, 50/60 Hz (see Notes 1, 2 and 3) 100 ms -11 1s -6.5 I A TSM 5s -3.4 300 s -1.4 900 s -1.3 Non-repetitive peak gate current, 2/10 s pulse, cathode commoned (see Note 1) I 10 A GSM Junction temperature T -55 to +150 C J Storage temperature range T -65 to +150 C stg NOTES: 1. Initially, the protector must be in thermal equilibrium with -40 C T 85 C. The surge may be repeated after the device returns J to its initial conditions. 2. These non-repetitive rated currents are peak values. The rated current values may be applied to any cathode-anode terminal pair. Above 85 C, derate linearly to zero at 150 C lead temperature. 3. These non-repetitive rated terminal currents are for the TISP8200M and TISP8201M together. Device (A) terminal positive current values are conducted by the TISP8201M and (K) terminal negative current values by the TISP8200M. MAY 1998 REVISED JULY 2019 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.