TISP83121D DUAL-GATE UNIDIRECTIONAL OVERVOLTAGE PROTECTOR TISP83121D Unidirectional P & N-Gate Protector Overvoltage Protection for Dual-Voltage Ringing SLICs Agency Recognition Programmable Protection Configurations up to 100 V Typically 5 Lines Protected by: Description Two TISP83121D + Diode Steering Networks UL File Number: E215609 High Surge Current 150 A, 10/1000 s 250 A, 10/700 s 8-SOIC Package (Top View) 500 A, 8/20 s 1 8 K K Pin Compatible with the LCP3121 50 % more surge current G1 2 7 A Functional Replacement in Diode Steering Applications G2 3 6 A Small Outline Surface Mount Package 5 K 4 K Description MD6XAYB The TISP83121D is a dual-gate reverse-blocking unidirectional For operation at the rated current values connect pins 1, 4, 5 and 8 together. thyristor designed for the protection of dual-voltage ringing SLICs (Subscriber Line Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and Device Symbol induction. A The device chip is a four-layer NPNP silicon thyristor structure which has an electrode connection to every layer. For negative overvoltage protection the TISP83121D is used in a common G2 anode configuration with the voltage to be limited applied to the cathode (K) terminal and the negative reference potential applied to the gate 1 (G1) terminal. For positive overvoltage protection the TISP83121D is used in a common cathode configuration with the voltage to be limited applied to the anode (A) terminal and the G1 positive reference potential applied to the gate 2 (G2) terminal. The TISP83121D is a unidirectional protector and to prevent K SD6XAKA reverse bias, requires the use of a series diode between the protected line conductor and the protector. Further, the gate reference supply voltage requires an appropriately poled series ................................................... UL Recognized Component diode to prevent the supply from being shorted when the TISP83121D crowbars. Under low level power cross conditions the TISP83121D gate current will charge the gate reference supply. If the reference supply cannot absorb the charging current its potential will increase, possibly to damaging levels. To avoid excessive voltage levels a clamp (zener or avalanche breakdown diode) may be added in shunt with the supply. Alternatively, a grounded collector emitter-follower may be used to reduce the charging current by the transistors H value. FE This monolithic protection device is made with an ion-implanted epitaxial-planar technology to give a consistent protection performance and be virtually transparent to the system in normal operation. How To Order Order As Device Package Carrier R (Embossed Tape Reeled) TISP83121DR-S TISP83121 D (8-pin Small-Outline) FEBRUARY 1999 REVISED JULY 2019 *RoHS Directive 2015/863, Mar 31, 2015 and Annex. Specifications are subject to change without notice. Users should verify actual device performance in their WARNING Cancer and Reproductive Harm specific applications. The products described herein and this document are subject to specific legal disclaimers as www.P65Warnings.ca.gov set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP83121D Unidirectional P & N-Gate Protector Absolute Maximum Ratings Rating Symbol Value Unit Repetitive peak off-state voltage, 0 C to 70 C V 100 V DRM Non-repetitive peak on-state pulse current (see Notes 1 and 2) 10/1000 s (GR-1089-CORE, open-circuit voltage wave shape 10/1000 s) 150 I A TSP 5/310 s (CCITT K20/21, open-circuit voltage wave shape 7 kV, 10/700 s) 250 8/20 s (ANSI C62.41, open-circuit voltage wave shape 1.2/50 s) 500 Non-repetitive peak on-state current, 50 Hz, halfwave rectified sinewave, (see Notes 1 and 2) 100 ms 22 1 s I 8 A TSM 900 s 3 Junction temperature T -40 to +150 C J Storage temperature range T -65 to +150 C stg NOTES: 1. Initially the protector must be in thermal equilibrium with 0 C < T < 70 C. The surge may be repeated after the device returns to J its initial conditions. For operation at the rated current value, pins 1, 4, 5 and 8 must be connected together. 2. Above 70 C, derate linearly to zero at 150 C lead temperature. Electrical Characteristics, T = 25 C (Unless Otherwise Noted) J Parameter Test Conditions Min Typ Max Unit I Off-state current V = 70 V, I = 0 1 A D d G Repetitive peak off- I V = V = 100 V, I = 0, 0 C to 70 C 10 A DRM d DRM G state current T = 0 to 70 C 300 J I Holding current I = 1 A, di/dt = -1A/ms T = 25 C 90 mA H T J T = 70 C 60 J I Reverse current V = 0.3 V 1 mA R R I Gate G1 trigger current I = +1 A, t = 20 s +200 mA G1T T p(g) I Gate G2 trigger current I = +1 A, t = 20 s -180 mA G2T T p(g) V G1-K trigger voltage I = +1 A, t = 20 s +1.8 V G1T T p(g) V G2-A trigger voltage I = +1 A, t = 20 s -1.8 V G2T T p(g) Anode-cathode off- C f = 1 MHz, V = 1 V rms, V = 5 V, I = 0 (see Note 3) 100 pF AK d D G state capacitance NOTE 3: These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured device terminals are a.c. connected to the guard terminal of the bridge. Thermal Characteristics Parameter Test Conditions Min Typ Max Unit T = 25 C, EIA/JESD51-3 PCB, A R Junction to free air thermal resistance 105 C/W JA EIA/JESD51-2 environment, I = I T TSM(900) FEBRUARY 1999 REVISED JULY 2019 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.