Data Sheet ACPL-0873 Three-Channel Digital Filter for Sigma-Delta Modulators Description Features The Broadcom ACPL-0873 is a 3-channel digital filter Direct interface between Isolated Sigma-Delta Modulator and MCU/DSP designed specifically for Second Order Sigma-Delta Modulators in voltage and current sensing. Each input Three individual digital filters channel can receive an independent Sigma-Delta (-) Fast over-range detection modulator bit stream. The bit streams are processed by Offset calibration three individual digital decimation filters. Features of the Channel 1 MCLK clock detection at power up digital filter include four decimation ratios for Sinc2 mode Programmable input configuration and three decimation ratios for Sinc3 mode, offset SPI-compatible interface calibration, and fast over-range detection. Compact surface-mount QFN-20 5 mm 5 mm The ACPL-0873 outputs an over-current signal for three Specifications channels, signaling over-voltage/current conditions. Operating temperature 40C to 125C Through SPI compatible interface, ACPL-0873 can directly SPI clock frequency up to 17 MHz connect to a microcontroller to output 16 bits digital filter Modulator clock frequency up to 25 MHz data and write/read filter registers. Applications Motor phase and rail current sensing Power inverter current and voltage sensing Industrial process control Data acquisition systems General voltage or current sensing Broadcom ACPL-0873-DS103 February 25, 2019ACPL-0873 Data Sheet Three-Channel Digital Filter for Sigma-Delta Modulators Schematic Diagram and Package Pin Out Figure 1: Schematic Diagram and Package Pin Out NOTE: 0.1-F and 1-F bypass capacitors between VDD and GND are recommended. Table 1: Pin Function Description Pin No. Pin Name Description Type 1 MCLK1 Channel 1 Clock Input 2 MDAT1 Channel 1 Data. Input Data on MDAT1 is clocked in on the rising edge of MCLK1. Input 3 MCLK2 Channel 2 Clock Input 4 MDAT2 Channel 2 Data. Input Data on MDAT2 is clocked in on the rising edge of MCLK2. Input 5 NC Not connected 6 NC Not connected 7CS Chip Select, Active Low of Chip Select for SPI interface and digital filter conversion start on the falling Input edge of CS. 8 SCLK SPI Clock input Input 9 GND Ground Power Input 10 MOSI SPI data Master Out Slave In Input 11 MISO SPI data Master In Slave Out Output 12 OC Over-Current Output 13 DR Data Ready. Output 1. DR pin High indicates Digital Filter data conversion ready. 2. DR pin is automatically cleared to Low when CS goes high. 14 INT Interrupt, Active Low. Output 15 NC Not connected 16 NC Not connected 17 RST Reset. Active Low, period 100 s at least. Input 18 VDD Power Supply Power Input 19 MDAT3 Channel 3 Data. Input Data on MDAT3 is clocked in on the rising edge of MCLK3. Input 20 MCLK3 Channel 3 Clock Input Broadcom ACPL-0873-DS103 2