BCM8727 Brief DUAL-CHANNEL 10-GBE SFI-TO-XAUI TRANSCEIVER WITH EDC SUMMARY OF BENEFITS FEATURES Dual-channel SFI-to-XAUI transceiver Single-reference clock input enables use of low-cost 156.25 MHz oscillator. Integrated microcontroller and AGC with a wide dynamic range Supports low-cost SFP+ copper twin-ax up to 15m Supports SFP+ SR, LR, and LRM optical interfaces and up to LRM mode supports 300m of Multimode Fiber (MMF), 15m of direct attached copper exceeding the IEEE 802.3aq standard. Programmable amplitude control on 10G serial transmitter PMD transmit preemphasis for flexible placement of Physical interface Layer (PHY) Standard two-wire Broadcom Serial Interface (BSC) support Support for module present detection and configuring of for external E2, XFP, SFP, SFP+ BCM8727 accordingly MDIO interface compliant to IEEE802.3ae Clause 45 with Multirate 10 GbE and 1 GbE support for legacy interfaces extended indirect address register access Support for XFP/XFI interfaces APPLICATIONS Physical Medium Dependent (PMD) interface: serial 10.3125 Gbps CML High-density Ethernet Switching and Routing Platforms PCS 64B/66B scrambler/descrambler Next-generation Blade Servers XGXS 8B/10B error detection ENDEC SFP+ optical SR, LR, and LRM modules XAUI link synchronization/deskew SFP+ copper twin-ax 4-lane XAUI interface (3.125 Gbps) Built-In Self-Test (BIST) on 10G serial and XAUI interfaces Power dissipation: 2.4W Core supply1.0V, I/O3.3V Small 19 mm x 19 mm BGA package, 1-mm ball pitch BCM8727 Functional Block Diagram BCM8727 10.3125 XAUI Interface 1 SFI 1 SFP+ Gbps LRM- EDC MAC/ Switch 10.3125 SFI 2 SFP+ XAUI Interface 2 Gbps LRM- MDC MDIO EDC Management Interface RS XGXS XGXS PCS/PMAOVERVIEW BCM8727 Block Diagram The BCM8727 is a dual-channel 10-GbE SFI-to-XAUI transceiver that On-chip clock synthesis is performed by the high-frequency, low-jitter, incorporates an Electronic Dispersion Compensation (EDC) equalizer Phase-Locked Loops (PLLs) for the PMD and XAUI output retimers. supporting SFP+ line-card applications. Individual PMD and XAUI clock recovery is performed on the device by synchronizing directly to the respective incoming data streams. An The BCM8727 is a multirate PHY targeted for SMF, MMF, or copper external 156.25 MHz reference clock input is required for each port. twin-ax applications interfacing to both limiting-based and linear-based SFP+ and SFP modules. The BCM8727 is fully compliant to the 10-GbE The BCM8727 Ethernet LRM PHY device is a fully integrated SerDes IEEE 802.3aq standard and also supports 1000BASE-X for 1-GbE (10.3125 Gbps) interface device performing the extension functions for operation. a 10-Gigabit serial Ethernet Reconciliation Sublayer (RS) interface. The XGXS, PCS, and PMA functions include 8B/10B coding, 64B/66B The BCM8727 is developed using an all-DSP high-speed front-end coding, SerDes, Clock Multiplication Unit (CMU), and Clock and Data providing the highest performance and most flexibility for line-card Recovery (CDR). designers. An on-chip microcontroller implements the control algorithm for the DSP core. The BCM8727 is available in a 19 mm x 19 mm, 1 mm pitch, 324-pin BGA, RoHS-compliant package. The BCM8727 supports a footprint- compatible layout with the BCM8726 dual LRM PHY. Broadcom , the pulse logo, Connecting everything , and the Connecting everything logo are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. BROADCOM CORPORATION Phone: 949-926-5000 5300 California Avenue Fax: 949-926-5203 Irvine, California 92617 E-mail: info broadcom.com Web: www.broadcom.com 2009 by BROADCOM CORPORATION. All rights reserved. 8727-PB00-R 03/16/09 XAOP 8B/10B Serializer Encoder XAON 64/66B PDIP Synchronizer CDR and MMF EDC AGC Descrambler Deserializer DSP Core PDIN Decoder XDOP 8B/10B Serializer Encoder XDON 322.26M 312.5M 156.25M CMU 156.25 MHz REFCLKP REFCK RefClk 32K REFCLKN Block ROM uC 312.5M 16K 312.5M SPI SPI Sync. Detect L RAM ane XAIP Lane Syn DLL and c 322.26M nt Alignme D XAIN eserializer 8B/10B FIFO Decoder 64/66B CMU and PDOP Encoder Serializer PDON Scrambler Sync. Detect Lane XDIP DLL and Lane Sync Alignment XDIN Deserializer 8B/10B FIFO Decoder XAOP 8B/10B Serializer Encoder XAON 64/66B PDIP Synchronizer CDR and MMF EDC AGC Descrambler Deserializer DSP Core PDIN Decoder XDOP 8B/10B Serializer Encoder XDON 322.26M 312.5M 156.25M CMU REFCK RefClk 32K Block ROM uC 312.5M 16K 312.5M Sync. De SPI SPI tect Lane RAM XAIP Lane Sync DLL and 322.26M Alignment Deserializer XAIN 8B/10B FIF O Decod er 64/66B CMU and PDOP Encoder Serializer PDON Scrambler Sync. Detect Lane XDIP DLL and Lane Sync Alignment XDIN Deserializer 8B/10B FIFO Decoder MDIO Management MDC and PRTAD 4:1 Control RSTB Interface LASI SDA BSC Serial OPRXLOS Optics SCL Interface ABS Control MOD and OPTXENB Status JTAG OPRSTB 3.125 Gbps 3.125 Gbps 3.125 Gbps 3.125 Gbps Randomizer Randomizer Elastic FIFO Elastic FIFO Elastic FIFO Elastic FIFO Gearbox Gearbox Gearbox Gearbox 10.3125 Gbps 10.3125 Gbps