MGA-638P8 High Linearity Low Noise Amplifi er Data Sheet Description Features Avago Technologies MGA-638P8 is an economical, easy- High linearity performance. to-use GaAs MMIC Low Noise Amplifi er (LNA). This LNA Low Noise Figure. has low noise and high linearity achieved through the 1 GaAs E-pHEMT Technology . use of Avago Technologies proprietary 0.25 m GaAs Enhancement-mode pHEMT process. It is housed in the Low cost small package size. 3 miniature 2.0 x 2.0 x 0.75 mm 8-pin Dual-Flat-Non-Lead Integrated with active bias and option to access FET (DFN) package. The device is designed for optimum use gate. from 2.5 GHz up to 4.0 GHz. The compact footprint and Integrated power down control pin. low profi le coupled with low noise, high gain and high linearity make this an ideal choice as a low noise amplifi er Specifi cations for cellular infrastructure applications such as LTE, GSM, CDMA, W-CDMA, CDMA2000 & TD-SCDMA. For optimum 2.5 GHz 4.8 V, 84 mA performance at lower frequency from 450 MHz up to 1.5 17.3 dB Gain GHz, MGA-636P8 is recommended. For optimum perfor- 0.87 dB Noise Figure mance from 1.5 GHz up to 2.5 GHz, MGA-637P8 is recom- mended. All these 3 products, MGA-636P8, MGA-637P8 14 dB Input Return Loss and MGA-638P8 share the same package and pinout con- 22.6 dBm Input IP3 fi guration. 22.2 dBm Output Power at 1 dB gain compression Pin Confi guration and Package Marking Applications 3 2.0 x 2.0 x 0.75 mm 8-lead DFN Cellular infrastructure applications such as LTE, GSM, 1 8 CDMA, W-CDMA, CDMA2000 & TD-SCDMA. 8 1 7 7 2 Other low noise applications. 2 38X GND 6 3 6 3 Note: 5 4 1. Enhancement mode technology employs positive Vgs, thereby 5 4 eliminating the need of negative gate voltage associated with con- ventional depletion mode devices. TOP VIEW BOTTOM VIEW Pin 1 Not Used Pin 5 Vbias1 Pin 2 RFinput Pin 6 PwrDwn Pin 3 Vbias2 Pin 7 RFoutput Pin 4 Not Used Pin 8 Not Used Center paddle GND Attention: Observe precautions for handling electrostatic sensitive devices. Note: Package marking provides orientation and identifi cation ESD Machine Model = 100 V 38 = Product Code ESD Human Body Model = 350 V X = Month Code Refer to Avago Application Note A004R: It is recommended to ground Pin1, 4 and 8 which are Not Used. Electrostatic Discharge, Damage and Control. 1 Simplifi ed Schematic Vdd C6 R2 C4 L3 L2 1 8 NU NU C1 C2 RFin RFout 2 7 RFinput RFoutput 3 6 L1 Bias Vbias2 PwrDwn 4 5 NU Vbias1 C3 R1 Rb C7 C8 C5 Vbias1 PwrDwn Note: 1. Device is turned ON when PwrDwn pin is applied with 0 V or left open. Device is turned OFF when PwrDwn pin is applied with 3.3 V 1 Absolute Maximum Rating T =25 C Thermal Resistance A 2 Symbol Parameter Units Absolute Maximum Thermal Resistance (V = 4.8 V, I = 84 mA) dd dd V Device Voltage, V 5.5 dd = 67C/W RF output to ground jc Notes: I Drain Current mA 125 dd 1. Operation of this device in excess of any of Vbias1 Bias Voltage V 5.5 these limits may cause permanent damage. 2. Thermal resistance measured using Infra-Red V Power Down Voltage V 5.5 pwrDwn Measurement Technique. P CW RF Input Power dBm +24 in,max 3. Power dissipation with unit turned on. Board temperature T is 25 C. Derate at 14.9 mW/C C P Total Power Dissipation W 0.61 diss for T > 105.8 C. c T Junction Temperature C 150 j T Storage Temperature C -65 to 150 STG 2