PEX 8696, PCI Express Gen 2 Switch, 96 Lanes, 24 Ports TM Highlights The ExpressLane PEX 8696 device offers Multi-Host PCI Express PEX 8696 General Features switching capability enabling users to connect multiple hosts to their o 96-lane, 24-port PCIe Gen2 switch respective endpoints via scalable, high bandwidth, non-blocking - Integrated 5.0 GT/s SerDes 2 interconnection to a wide variety of applications including servers, o 35 x 35mm , 1156-ball FCBGA package storage systems, and communications platforms. The PEX 8696 is o Typical Power: 10.2 Watts well suited for fan-out, aggregation, and peer-to-peer applications. PEX 8696 Key Features o Standards Compliant Multi-Host Architecture - PCI Express Base Specification, r2.0 The PEX 8696 employs an enhanced version of PLXs field tested PEX 8648 (backwards compatible w/ PCIe r1.0a/1.1) PCIe switch architecture, which allows users to configure the device in - PCI Power Management Spec, r1.2 legacy single-host mode or multi-host mode with up to eight host ports - Microsoft Vista Compliant - Supports Access Control Services capable of 1+1 (one active & one backup) or N+1 (N active & one backup) - Dynamic link-width control host failover. This powerful architectural enhancement enables users to build - Dynamic SerDes speed control PCIe based systems to support high-availability, failover, redundant and o High Performance clustered systems. performancePAK 9 Read Pacing (bandwidth throttling) 9 Multicast High Performance & Low Packet Latency 9 Dynamic Buffer/FC Credit Pool The PEX 8696 architecture supports packet cut-thru with a maximum - Non-blocking switch fabric latency of 176ns (x16 to x16). This, combined with large packet memory, - Full line rate on all ports flexible common buffer/FC credit pool and non-blocking internal switch - Packet Cut-Thru with 176ns max packet latency (x16 to x16) architecture, provides full line rate on all ports for performance-hungry - 2KB Max Payload Size applications such as servers and switch fabrics. The low latency enables o Flexible Configuration applications to achieve high throughput and performance. In addition to low - Ports configurable as x1, x2, x4, x8, x16 latency, the device supports a packet payload size of up to 2048 bytes, - Registers configurable with strapping 2 enabling the user to achieve even higher throughput. pins, EEPROM, I C, or host software - Lane and polarity reversal - Compatible with PCIe 1.0a PM Data Integrity o Multi-Host & Fail-Over Support The PEX 8696 provides end-to-end CRC (ECRC) protection and Poison bit - Configurable Non-Transparent (NT) port support to enable designs that require end-to-end data integrity. PLX also - Failover with NT port - Up to Eight upstream/Host ports with 1+1 supports data path parity and memory (RAM) error correction circuitry or N+1 failover to other upstream ports throughout the internal data paths as packets pass through the switch. o Quality of Service (QoS) - Eight traffic classes per port Flexible Configuration - Weighted round-robin source The PEX 8696s 24 ports can be configured to lane widths of x1, x2, x4, x8, port arbitration o Reliability, Availability, Serviceability or x16. Flexible buffer allocation, x4 x8 visionPAK along with the device s flexible 9 Per Port Performance Monitoring packet flow control, maximizes Per port payload & header counters PEX 8696PEX 8696 PEX 8696PEX 8696 PEX 8696PEX 8696 PEX 8696PEX 8696 throughput for applications where 9 SerDes Eye Capture more traffic flows in the 9 Error Injection and Loopback - 4 Hot Plug Ports with native HP Signals downstream, rather than upstream, 2 23 x4 7 x8 8 x4 - All ports hot plug capable thru I C direction. Any port can be designated (Hot Plug Controller on every port) x16 x8 as the upstream port, which can be - ECRC and Poison bit support changed dynamically. Figure 1 - Data Path parity - Memory (RAM) Error Correction shows some of the PEX 8696s PEX 8696PEX 8696 PEX 8696PEX 8696 PEX 8696PEX 8696 PEX 8696PEX 8696 - INTA and FATAL ERR signals common port configurations in - Advanced Error Reporting legacy Single-Host mode. - Port Status bits and GPIO available 6 x8 10 x4 10 x8 - Per port error diagnostics Figure 1. Common Port Configurations - JTAG AC/DC boundary scan PLX Technology, www.plxtech.com Page 1 of 1 5/14/2009, Version 1.1 PEX 8696, PCI Express Gen 2 Switch, 96 Lanes, 24 Ports The PEX 8696 can also be configured in Multi-Host PEX 8696 allows the hosts to communicate their status mode where users can choose up to eight ports as to each other via special door-bell registers. In failover host/upstream ports and assign a desired number of mode, if a host fails, the host designated for failover will downstream ports to each host. In Multi-Host mode, a disable the upstream port attached to the failing host and virtual switch is created for each host port and its program the downstream ports of that host to its own associated downstream ports inside the device. The domain. Figure 4a shows a two host system in Multi- traffic between the ports of a virtual switch is completely Host mode with two virtual switches inside the device isolated from the traffic in other virtual switches. Figure and Figure 4b shows Host 1 disabled after failure and 2 illustrates some configurations of the PEX 8696 in Host 2 having taken over all of Host 1s end-points. Multi-Host mode where each ellipse represents a virtual HosHostt 1 1 HoHosstt 2 2 HosHostt 1 1 HoHosstt 2 2 HosHostt 1 1 HoHosstt 2 2 HosHostt 1 1 HoHosstt 2 2 switch inside the device. x16 x16 x8 x8 x8 PEX 8696 PEX 8696 PEX 8696 PEX 8696 The PEX 8696 also provides several ways to PPPEPEEEXXX 86X 86 86 8696969696 PPPPEX 86EX 86EEXX 86 8696969696 EnEnEnEnd d d d EnEnEnEnd d d d EnEnEnEnd d d d EEEEnd nd nd nd EnEnEnEnd d d d EnEnEnEnd d d d EndEndEndEnd EnEnEnEndddd configure its registers. The PoPoPoPoiiiinnnntttt PoiPoiPoiPoinnnntttt PoPoPoPoiiiinnnntttt PoPoPoPoiiiinnnntttt PoPoPoPoiiiinnnntttt PoPoPoPoiiiinnnntttt PoPoPoPoiiiinnnntttt PoPoPoPoiiiinnnntttt Figure 4a. Multi-Host Figure 4b. Multi-Host Fail-Over device can be configured 2 x8, 4 x4 2 x8, 4x4 6 x4 6 x4 6 x4 4 x4s 8 x4s through strapping pins, 2 Hot Plug for High Availability I C interface, host Hot plug capability allows users to replace hardware software, or an optional PEPEPPEX 8EX 8X 86X 866966969696 PEPEX 86X 869696 PPEX 86EX 869696 modules and perform maintenance without powering serial EEPROM. This down the system. The PEX 8696 hot plug capability allows for easy debug 20 x4s 2 x8, 12 x4s Figure 2. Common Multi-Host Configurations feature makes it suitable for High Availability (HA) during the development applications. Four downstream ports include a Standard phase, performance monitoring during the operation Hot Plug Controller. If the PEX 8696 is used in an phase, and driver or software upgrade. application where one or more of its downstream ports connect to PCI Express slots, each ports Hot Plug Dual-Host & Failover Support Controller can be used to manage the hot-plug event of In Single-Host mode, the PEX 8696 supports a Non- its associated slot. Every port on the PEX 8696 is Transparent (NT) Port, which enables the equipped with a hot-plug control/status register to implementation of dual-host systems for redundancy support hot-plug capability through external logic via the and host failover capability. PPPrrriiimmmararary Hoy Hoy Hoststst SecoSecoSecondndndararary Hy Hy Hostostost PPPrrriiimmmararary Hosty Hosty Host SSSecoecoecondarndarndaryyy Ho Ho Hoststst 2 I C interface. CPUCPUCPU CPUCPUCPU The NT port allows systems CPUCPUCPU CPUCPUCPU to isolate host memory SerDes Power and Signal Management domains by presenting the RooRooRooRooRooRootttttt CoCoCoCoCoCommmmmmpppppplllllleeeeeexxxxxx The PEX 8696 supports software control of the SerDes processor subsystem as an outputs to allow optimization of power and signal endpoint rather than another strength in a system. The PLX SerDes implementation NTNT memory system. Base PPEX 86EX 869696 PPEX 86EX 869966 supports four levels of power off, low, typical, and Non-Non-TrTransanspparareenntt address registers are used PortPort high. The SerDes block also supports loop-back modes to translate addresses EnEnEnEnd d d d EnEnEnEnd d d d EnEnEnEnd d d d and advanced reporting of error conditions, which EnEnEnEnd d d d EnEnEnEnd d d d EnEnEnEnd d d d doorbell registers are used PointPointPointPoint PointPointPointPoint PoPoPoPoiiiinnnntttt PointPointPointPoint PointPointPointPoint PoPoPoPoiiiinnnntttt enables efficient management of the entire system. to send interrupts FiFiguregure 3. 3. Non Non--TTrranansparensparentt Port Port between the address Interoperability domains and scratchpad registers (accessible by both The PEX 8696 is designed to be fully compliant with the CPUs) allow inter-processor communication (see Figure PCI Express Base Specification r2.0, and is backwards 3). compatible to PCI Express Base Specification r1.1 and r1.0a. Additionally, it supports auto-negotiation, lane Multi-Host & Failover Support reversal, and polarity reversal. Furthermore, the PEX In Multi-Host mode, PEX 8696 can be configured with 8696 is tested for Microsoft Vista compliance. All PLX up to eight upstream host ports, each with its own switches undergo thorough interoperability testing in dedicated downstream ports. The device can be PLXs Interoperability Lab and compliance testing at configured for 1+1 redundancy or N+1 redundancy. The the PCI-SIG plug-fest. PLX Technology, www.plxtech.com Page 2 of 2 5/14/2009, Version 1.1