WM8196SCDS/V

WM8196 w (8 + 8) Bit Output 16-bit CIS/CCD AFE/Digitiser DESCRIPTION FEATURES 16-bit ADC The WM8196 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals 12MSPS conversion rate from CCD sensors or Contact Image Sensors (CIS) at pixel Low power 320mW typical sample rates of up to 12MSPS. 5V single supply or 5V/3.3V dual supply operation The device includes three analogue signal processing Single or 3 channel operation channels each of which contains Reset Level Clamping, Correlated double sampling Correlated Double Sampling and Programmable Gain and Programmable gain (8-bit resolution) Offset adjust functions. Three multiplexers allow single Programmable offset adjust (8-bit resolution) channel processing. The output from each of these Programmable clamp voltage channels is time multiplexed into a single high-speed 16-bit Analogue to Digital Converter. The digital output data is 8 or 4-bit wide multiplexed data output formats available in 8 or 4-bit wide multiplexed format. Internally generated voltage references 28-lead SSOP package An internal 4-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS Serial control interface signals or during Reset Level Clamping to clamp CCD signals. An external reference level may also be supplied. APPLICATIONS ADC references are generated internally, ensuring optimum Flatbed and sheetfeed scanners performance from the device. USB compatible scanners Using an analogue supply voltage of 5V and a digital Multi-function peripherals interface supply of either 5V or 3.3V, the WM8196 typically High-performance CCD sensor interface only consumes 300mW when operating from a single 5V supply. BLOCK DIAGRAM VRLC/VBIAS VSMP MCLK AVDD DVDD1 DVDD2 VRX VRB VRT w CL R V TIMING CONTROL WM8196 S S VREF/BIAS R 8 M OFFSET OEB G U DAC X B RINP RLC CDS + PGA + M U I/P SIGNAL R 8 M OP 0 X POLARITY G U OP 1 X ADJUST B OP 2 DATA OP 3 M 16- I/O OP 4 GINP PORT RLC CDS + PGA + U BIT OP 5 X ADC 8 OP 6 OFFSET 8 I/P SIGNAL DAC OP 7 /SDO POLARITY ADJUST BINP RLC CDS + PGA + 8 OFFSET 8 I/P SIGNAL DAC POLARITY CONFIGURABLE SEN ADJUST SERIAL SCK CONTROL SDI RLC 4 INTERFACE RLC/ACYC DAC DGND AGND1 AGND2 Production Data, October 2008, Rev 4.6 WOLFSON MICROELECTRONICS plc Copyright 2008 Wolfson Microelectronics plc To receive regular email updates, sign up at WM8196 Production Data TABLE OF CONTENTS DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 THERMAL PERFORMANCE .................................................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 INPUT VIDEO SAMPLING............................................................................................. 8 OUTPUT DATA TIMING ................................................................................................ 8 SERIAL INTERFACE ................................................................................................... 10 INTERNAL POWER ON RESET CIRCUIT ..........................................................11 DEVICE DESCRIPTION.......................................................................................13 INTRODUCTION.......................................................................................................... 13 INPUT SAMPLING....................................................................................................... 13 RESET LEVEL CLAMPING (RLC) ............................................................................... 13 CDS/NON-CDS PROCESSING ................................................................................... 14 OFFSET ADJUST AND PROGRAMMABLE GAIN....................................................... 15 ADC INPUT BLACK LEVEL ADJUST .......................................................................... 16 OVERALL SIGNAL FLOW SUMMARY ........................................................................ 16 CALCULATING OUTPUT FOR ANY GIVEN INPUT .................................................... 16 OUTPUT FORMATS.................................................................................................... 17 CONTROL INTERFACE .............................................................................................. 18 TIMING REQUIREMENTS........................................................................................... 19 PROGRAMMABLE VSMP DETECT CIRCUIT ............................................................. 19 REFERENCES............................................................................................................. 20 POWER SUPPLY ........................................................................................................ 20 POWER MANAGEMENT ............................................................................................. 20 LINE-BY-LINE OPERATION ........................................................................................ 21 OPERATING MODES.................................................................................................. 22 OPERATING MODE TIMING DIAGRAMS ................................................................... 23 DEVICE CONFIGURATION .................................................................................26 REGISTER MAP .......................................................................................................... 26 REGISTER MAP DESCRIPTION................................................................................. 27 APPLICATIONS INFORMATION .........................................................................30 RECOMMENDED EXTERNAL COMPONENTS........................................................... 30 RECOMMENDED EXTERNAL COMPONENT VALUE ................................................ 30 PACKAGE DIMENSIONS ....................................................................................31 IMPORTANT NOTICE ..........................................................................................32 ADDRESS:................................................................................................................... 32 PD Rev 4.6 October 2008 w 2