CCLD-033 57mm SMD LVDS Clock Oscillator CCLD-033 Model 57 mm SMD, 3.3V, LVDS Model CCLD-033 is a 77.760 MHz to 161.000 MHz LVDS Clock Oscillator operating at 3.3 Volts. The oscillator utilizes a High Q Third Overtone crystal design providing very low Jitter and Phase Noise. No Sub-Harmonics are present in the Output Signal. Applications: Digital Video 57mm SMD SONET/SDH/DWDM Storage Area Networks Broadband Access Ethernet, Gigabit Ethernet Rev: S Date: 26-Aug-2021 Page 1 of 3 16850 Oriole Road Fort Myers, Florida 33912 CRYSTEK Phone: 239-561-3311 800-237-3061 CORPORATION www.crystek.com CCCLD-033 57mm SMD LVDS Clock Oscillator CCLD-033 Model 57 mm SMD, 3.3V, LVDS Frequency Range: 77.760 MHz to 161.000 MHz Frequency Stability Options(ppm): 20, 25, 50, 100 Temperature Range: (standard) 0C to +70C (Option M) -20C to +70C (Option X) -40C to +85C Storage: -45C to 90C Input Voltage: 3.3V 0.3V Input Current: 66mA Max Standby Current: 30uA Max Output: Differential LVDS Symmetry: 45/55% Max zero crossing point Rise/Fall Time: 1ns Max (20% to 80%) Load: 100 Ohms Connected between OUT and COUT Output Drive Capability (see Note 1): Zero Impedance Bipolar Process Logic: Output Voltage Levels 0=0.90 Min, 1.10 Typical 1=1.43 Typical, 1.60 Max Differential Output Voltage: 247mV Min, 454mV Max Disable Time: 200ns Max Start-up Time: 10ms Max Phase Jitter: 12kHz~80MHz 0.5ps Typical, 1ps RMS Max Phase Noise: (See Plot Below) Sub-harmonics: None st Aging: <3ppm 1 year, <1ppm every year thereafter Note 1: Internal Driver will change to Finite Impedance CMOS Process. Consult factory for additional details and changeover date. Typical Phase Noise Plot Rev: S Date: 26-Aug-2021 Page 2 of 3 16850 Oriole Road Fort Myers, Florida 33912 CRYSTEK Phone: 239-561-3311 800-237-3061 CORPORATION www.crystek.com C