Neuron 6050 TM IP Processor for IzoT Enabled Devices The Neuron 6050 is optimized for 5 12 Comm External modernizing and consolidating smart / I / O / Port Transformer control devices and networks. 2-6 Serial NVM It is a key product in Echelons / Memory (SPI) IRQ CPU Interface IzoT Platform the most comprehensive and open control networking platform for the Industrial APP CPU RAM Internet of Things (IIoT). It offers options for (64K x 8) Neuron 6050 Key Features backward compatibility with LONWORKS NET CPU while adding native IP addressing at the Upto 80MHz system clock, 64KB device level and consolidating multiple RAM and 16KB ROM on-chip ROM control protocols on the same device. memories (16K x 8) MAC CPU The Neuron 6050 Processor incorporates Support for larger external communication and control functions on Clock, Reset, JTAG afl sh memories, up to 256KB and Service a single chip, in both hardware and applications rfi mware, to facilitate the design of 5 LonTalk , LonTalk/IP or BACnet/IP devices. Support for up to 254 Network Its flexible 5-pin communications port Variables (NVs), 127 aliases can be configured to interface with a wide Figure 1: Neuron 6050 Processor 16-fold increase in address table variety of transceivers including twisted- entries, up to 254 entries pair, RF, IR, fiber-optics, and coaxial at a Multi-protocol Operation, Future wide range of data rates. Proonfi g and Backward Compatibility User programmable interrupts, hardware UART, 12 I/O pins with The Neuron 6050 Processor includes The Neuron 6050 Processor supports up 35 programmable standard I/O 3 independent 8-bit logical processors to four different modes of operation, as models to manage the physical MAC layer, the shown in Figure 2, allowing device makers network, and the user application. These unprecedented flexibility in creating control 5-pin network communications are called the Media-Access Control (MAC) devices for a wide variety of applications port with 3.3V drive and processor, the network (NET) processor, using one common development effort. 5V-tolerant pins. and the application (APP) processor, Backward compatibility and future proonfi g respectively (see Figure 1). At higher system can both be met using a common platform Unique 48-bit IEEE MAC ID clock rates, a fourth processor called the based on the Neuron 6050 Processor in every device for network IRQ CPU can be used to handle interrupts. family. installation and management 7mm x 7mm 48-pin QFN package, -40C to +85C www.echelon.com Preliminary XIN XOUT RST~ SVC~The pins for the Neuron 6050 Processors communications devices that are fully compatible with LonTalk applications port drive a 3.3V signal and are 5V input-tolerant. Thus, the while supporting native IP addressing at the device level. In Neuron 6050 Processor is compatible with 3.3V transceivers this mode, the network layer has been enhanced to support and with 5V transceivers that have TTL-compatible input. translation between LonTalk addresses and IP addresses in a manner that is transparent to both the LonTalk application The Neuron 6050 Processor is compatible with transceivers above and the network below. This allows LonTalk compatible for TP/XF-1250 and EIA-485 channels, and can be used applications to run unmodified over a variety of media types with the LONWORKS LPT-11 Link Power Transceiver. It also while gaining IP addressing at the device level. supports a variety of other channels used with previous- generation Neuron Chips, such as RF, IR, fiber-optic, and In the BACnet/IP mode, LonTalk layers 4-6 services are coax. It does not, however, support a TP/XF-78 channel. To used to create BACnet/IP devices borrowing from a rich set support a TP/FT-10 channel, use an Echelon Free Topology of LONMARK services and prolfi es. LONMARK compatible Smart Transceiver (FT 6050 or FT 5000 Smart Transceiver) applications can now run unmodified over a variety of channel to support a PL-20 power line channel, use an Echelon types, and present their LONMARK interfaces as native Power Line Smart Transceiver (PL 3120/3150/3170 Smart BACnet Objects, thus pushing BACnet/IP all the way down Transceiver). Echelons Smart Transceivers integrate the to the simplest of devices. Provisioning and commissioning transceiver for the channel type and the Neuron core into a of BACnet/IP devices is now possible with available and single chip, which enables smaller designs and provides cost powerful LONWORKS commissioning tools. Devices thus savings. provisioned are fully compatible and discoverable using industry standard, BTL-certified BACnet management clients. The Neuron core in the Neuron 6050 Processor uses the same instruction set and architecture as the previous- And finally, in the Any IP mode, the Neuron 6050 Processor generation Neuron core, including instructions for hardware allows any control protocol to be modernized with IP multiplication and division. The Series 6050 Neuron core addressing transported over a variety of channel types. is source code compatible with applications written for the Enhanced Performance Series 5000 and 3100 Neuron core. Applications written for Fast system clock. The internal system clock for the Neuron the Series 5000 and 3100 Neuron core must be recompiled 6050 Processor can be user configured to run from 5MHz to with the IzoT NodeBuilder Software before they can be used 80MHz. The required external crystal provides a 10MHz clock with the Neuron 6050 Processor. frequency, and an internal PLL boosts the frequency to a The Neuron 6050 Processor uses Neuron firmware version maximum of 80MHz as the internal system clock speed. The 21 or later. Firmware versions prior to version 21 are not fast clock is the same as what is available with the Neuron compatible with the Neuron 6050 Processor. The Neuron Processor however, the Neuron 3120/3150 core divided rfi mware is loaded into RAM from off chip flash. The Neuron the external oscillator frequency by two to create the internal 6050 Processor firmware can be upgraded over the network. system clock. Hence, a Neuron 3120/3150 core running with a 10MHz external crystal had a 5MHz internal system clock. A Neuron 6050 Processor running with an 80MHz internal clock is thus 16 times faster than a 10MHz Neuron 3120/3150 core running with a 5MHz internal system clock. The 5MHz system clock mode in the Neuron 6050 Processor provides backward compatibility to support time-critical applications designed for the 10MHz Neuron 3150 or Neuron 3120 processor. The Neuron core inside the Neuron 6050 Processor includes a built-in hardware multiplier and divider to increase the performance of arithmetic operations. Support for large number of network variables. Interrupts. The Neuron 6050 Processor lets developers denfi e application interrupts to handle asynchronous events triggered by selected state changes on any of the 12 I/O pins, Figure 2: Neuron 6050 Modes of Operation by on-chip hardware timer-counter units, or by an on-chip high-performance hardware system timer. An application In the LonTalk mode, the Neuron 6050 Processor runs the uses the Neuron C interrupt() clause to denfi e the interrupt LonTalk stack down to the MAC layer and is fully backward condition and the interrupt task that handles the condition. compatible with devices running the LonTalk stack, including The Neuron C program runs the interrupt task whenever the devices based on the Neuron 3120, Neuron 3150 or FT interrupt condition is met. See the Neuron C Programmers 3120/3150/5000 Smart Transceiver. Guide for more information about writing interrupt tasks and handling interrupts. In the LonTalk/IP mode, the Neuron 6050 Processor preserves the services offered by LonTalk layers 4-6, replacing layers 2-3 with UDP/IP. This allows the creation of