PI6C20800B PI6C4911505-04 High Performance 1:5 LVPECL Fanout Buffer Features Description 5 LVPECL outputs e Th PI6C4911505-04 is a high performance fanout buffer device - which supports up to 1.5GHz frequency. The device has 2 select - Up to 1.5GHz output frequency able clock inputs that can accept most differential and single Ultra low additive phase jitter: < 0.03 ps (typ) (differential ended clock sources. This device is ideal for systems that need to 156.25MHz, 12KHz to 20MHz integration range) distribute low jitter clock signals to multiple destinations. Two selectable inputs Low delay from input to output (Tpd typ. 1.5ns) Applications 2.5V/3.3V power supply Networking systems including switches and Routers Industrial temperature support High frequency backplane based computing and telecom TSSOP-20 package platforms Block Diagram Pin Configuration (20-Pin TSSOP) Pulldown nEN D Q Q0 20 1 V DD LE Pulldown 19 nEN nQ0 2 CLK0 Pullup 0 Q 0 nCLK0 Q1 3 18 V nQ0 DD Pulldown 1 CLK1 Q1 17 nQ1 4 NC Q n 1 16 CLK1 Q2 5 Q Pulldown 2 CLK SEL nQ2 nQ2 15 6 CLK0 Q3 14 Q3 7 nCLK0 Q n 3 nQ3 8 13 NC Q 4 Q n 4 12 Q4 9 CLK SEL 11 nQ4 10 V EE www.pericom.com PI6C4911505-04 Rev A 10/31/12 1 12-0269PI6C4911505-04 High Performance 1:5 LVPECL Fanout Buffer Pinout Table Pin Pin Name Type Description Q0 1, 2 Output LVPECL output clock nQ0 Q1 3, 4 Output LVPECL output clock nQ1 Q2 5, 6 Output LVPECL output clock nQ2 Q3 7, 8 Output LVPECL output clock nQ3 Q4 9, 10 Output LVPECL output clock nQ4 11 V Power Negative power supply EE 12 CLK SEL Input Clock input source selection pin 13, 17 NC - No connect CLK0 14, 15 Input Differential clock input nCLK0 16 CLK1 Input CMOS clock input 18, 20 V Power Power supply DD Synchronizing clock enable. When LOW, clock 19 nEN Input outputs enabled. When HIGH, Q outputs are forced low, nQ outputs forced high. www.pericom.com PI6C4911505-04 Rev A 10/31/12 2 12-0269