OPMODEB0 25 VEE 16 26 OPMODEB1 15 VDD nQB0 27 nCLK1 14 28 QB0 13 CLK1 29 nQA2 12 nCLK0 30 QA2 CLK0 11 31 OPMODEA1 10 XTN 32 OPMODEA0 9 XT PI6C20800B PI6C49S1506 High Performance Differential Fanout Buffer Features Description 6 differential outputs with 2 banks e PTh I6C49S1506 is a high performance fanout buffer device - which supports up to 1.5GHz frequency. It also integrates a User configurable output signaling standard for each bank: unique feature with user configurable output signaling stan - LVDS or LVPECL or HCSL dards on per bank basis which provide great flexibilities to Up to 1.5GHz output frequency for differential outputs users. The device also uses Pericom s proprietary input detection Ultra low additive phase jitter: < 0.03 ps (typ) (differential technique to make sure illegal input conditions will be detected 156.25MHz, 12KHz to 20MHz integration range) and reefl cted by output states. This device is ideal for systems that need to distribute low jitter clock signals to multiple desti- Selectable reference inputs support either single-ended nations. or differential or Xtal Low skew between outputs within banks (<40ps) Low delay from input to output (Tpd typ. 1.5ns) Applications Separate Input output supply voltage for level shifting Networking systems including switches and Routers 2.5V / 3.3V power supply High frequency backplane based computing and telecom platforms Industrial temperature support TQFP-32 package Block Diagram Pin Configuration (32-Pin TQFP) OPMODEA 1:0 QA 0:2 3 VDDO 1 24 VDDO XT nQA1 2 23 QB1 OSC XTN OPMODEB 1:0 CLK0 QA1 3 22 nQB1 nCLK0 QB 0:2 3 VEE 4 21 VDDO CLK1 nCLK1 nQA0 5 20 QB2 QA0 6 19 nQB2 CLK SEL 1:0 CLK SEL0 7 18 CLK SEL1 Iref VEE 8 17 IREF PI6C49S1506 Rev C 08/11/14 14-0121 1PI6C49S1506 High Performance Differential Fanout Buffer Pinout Table Pin Pin Name Type Description 1, 21, 24 V Power Power supply pins for outputs DDO nQA1 Bank A differential output pair 1. Pin selectable 2,3 Output LVPECL/LVDS/HCSL interface levels. QA1 4, 16 V Power Connect to Negative power supply EE nQA0 Bank A differential output pair 0. Pin selectable 5, 6 Output LVPECL/LVDS/HCSL interface levels. QA0 7 CLK SEL0 Input Input clock source selection 8 V Power Negative power supply EE 9 XT Input XTAL input 10 XTN Output XTAL output CLK0 Input Differential clock input 11, 12 nCLK0 Input Differential clock input CLK1 Input Differential clock input 13, 14 nCLK1 Input Differential clock input 15 V Power Power supply pins for device core DD 17 IREF Output Reference current 18 CLK SEL1 Input Input clock source selection QB2 Bank B differential output pair 5. Pin selectable 19, 20 Output LVPECL/LVDS/HCSL interface levels. nQB2 nQB1 Bank B differential output pair 4. Pin selectable 22, 23 Output LVPECL/LVDS/HCSL interface levels. QB1 25 OPMODEB0 Input Bank B output selection pin 26 OPMODEB1 Input Bank B output selection pin nQB0 Bank B differential output pair 3. Pin selectable 27, 28 Output LVPECL/LVDS/HCSL interface levels. QB0 nQA2 Bank A differential output pair 2. Pin selectable 29, 30 Output LVPECL/LVDS/HCSL interface levels. QA2 31 OPMODEA1 Input Bank A output selection pin 32 OPMODEA0 Input Bank A output selection pin PI6C49S1506 Rev C 08/11/14 14-0121 2