PI6C557-03B PCIe 3.0 Clock Generator with 2 HCSL Outputs Features Description PCIe 3.0 compliant e Th PI6C557-03B is a spread spectrum clock generator compli - ant to PCI Express 3.0 and Ethernet requirements. e Th device is PCIe 3.0 Phase jitter - 0.45ps RMS (High Freq. Typ.) used for PC or embedded systems to substantially reduce Electro- LVDS compatible outputs magnetic Interference (EMI). Supply voltage of 3.3V 10% 25MHz crystal or clock input frequency e Th PI6C557-03B provides two differential (HCSL) or LVDS HCSL outputs, 0.8V Current mode differential pair spread spectrum outputs. e Th PI6C557-03B is configured to se - Jitter 35ps cycle-to-cycle (typ) lect spread and clock selection. Using Pericom s patented Phase- Locked Loop (PLL) techniques, the device takes a 25MHz crystal Spread of -0.5%, -0.75%, and no spread input and produces two pairs of differential outputs (HCSL) at Industrial temperature range 25MHz, 100MHz, 125MHz and 200MHz clock frequencies. It Spread Bypass option available also provides spread selection of -0.5%, -0.75%, and no spread. Spread and frequency selection via external pins Packaging: (Pb-free and Green) 16-pin TSSOP (L16) 16-pin QSOP (Q16) Block Diagram Pin Configuration (16-Pin TSSOP) VDD 2 1 16 S0 VDDX SS1:SS0 CLK0 2 2 15 S1 CLK0 Control CLK0 Logic S1:S0 Phase 14 SS0 3 CLK0 2 Lock Loop 13 X1/CLK 4 GNDA CLK1 X1/CLK 5 12 X2 VDDA CLK1 Crystal 25 MHz Driver 6 11 OE CLK1 crystal or clock X2 10 GNDX 7 CLK1 2 Pulling R R 9 Capacitors SS1 8 IREF GND OE All trademarks are property of their respective owners. www.pericom.com P-0.1 04/29/11 11-0062 1 PI6C557-03BPI6C557-03B PCIe 3.0 Clock Generator with 2 HCSL Outputs Pin Description Pin Pin Name I/O Type Description 1 S0 Input Select pin 0 (Internal pull-up resistor). See Table 1. 2 S1 Input Select pin 1 (Internal pull-up resistor). See Table 1. 3 SS0 Input Spread Select pin 0 (Internal pull-up resistor). See Table 2. 4 X1/CLK Input Crystal or clock input. Connect to a 25MHz crystal or single ended clock. 5 X2 Output Crystal connection. Leave unconnected for clock input. 6 OE Input Output enable. Internal pull-up resistor. 7 GNDX Power Crystal ground pin. 8 SS1 Input Spread Select pin 1 (Internal pull-up resistor). See Table 2. 9 IREF Output Precision resistor attached to this pin is connected to the internal current reference. 10 CLK1 Output HCSL compliment clock output 11 CLK1 Output HCSL clock output 12 VDDA Power Connect to a +3.3V source. 13 GNDA Power Output and analog circuit ground. 14 CLK0 Output HCSL compliment clock output 15 CLK0 Output HCSL clock output 16 VDDX Power Connect to a +3.3V source. Table 1: Output Select Table Table 2: Spread Selection Table S1 S0 CLK(MHz) SS1 SS0 Spread 0 0 25 0 0 No Spread 0 1 100 0 1 Down -0.5 1 0 125 1 0 Down -0.75 1 1 200 1 1 No Spread All trademarks are property of their respective owners. www.pericom.com P-0.1 04/29/11 11-0062 2