Product Information

FTLX1471D3BCV

FTLX1471D3BCV electronic component of Finisar

Datasheet
Fiber Optic Transmitters, Receivers, Transceivers PIN, 10GBASE-LR/LW 1200SM-LL-L 10km
Manufacturer: Finisar
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 131.56 ea
Line Total: USD 131.56

18 - Global Stock
Ships to you between
Tue. 28 May to Thu. 30 May
MOQ: 1  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
19 - WHS 1


Ships to you between Wed. 22 May to Tue. 28 May

MOQ : 10
Multiples : 10
10 : USD 165.0793
20 : USD 162.448
30 : USD 160.16
50 : USD 157.872
100 : USD 155.584
500 : USD 153.296
1000 : USD 151.008

Read More Specifications

     
Manufacturer
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RoHS - XON
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Wavelength
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Operating Supply Voltage
Minimum Operating Temperature
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Taric
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Additional Infomation About Product

Product Specification RoHS-6 Compliant 1G/10G 10km Datacom SFP+ Transceiver FTLX1471D3BCV PRODUCT FEATURES Hot-pluggable SFP+ footprint Supports rate selectable 1.25 Gb/s or 9.95 to 10.3 Gb/s bit rates Power dissipation < 1W RoHS-6 compliant (lead-free) Commercial temperature range -5C to 70C Single 3.3V power supply Maximum link length of 10km Uncooled 1310nm DFB laser APPLICATIONS Receiver limiting electrical interface 1000BASE-LX 1G Ethernet Duplex LC connector Built-in digital diagnostic functions 10GBASE-LR/LW 10G Ethernet Finisars FTLX1471D3BCV 1G/10G Dual-Rate SFP+ transceivers are designed for use in 1-Gigabit and 10-Gigabit Ethernet links up to 10km over singlemode fiber. They are 1 2 3 compliant with SFF-8431 , IEEE 802.3-2005 10GBASE-LR/LW and 1000BASE-LX . Digital diagnostics functions are available via a 2-wire serial interface, as specified in 4 SFF-8472 . This product is for applications specifically designed for 10G SFP+ ports and 1G/10G SFP+ ports and not native 1G SFP ports. The FTLX1471D3BCV is a limiting module, i.e., it employs a limiting receiver. Host board designers using an EDC PHY IC should follow the IC manufacturers recommended settings for interoperating the host- board EDC PHY with a limiting receiver SFP+ module. The optical transceivers are compliant per the RoHS Directive 2011/65/EU. See Finisar Application Note AN-2038 for more details. PRODUCT SELECTION FTLX1471D3BCV Finisar Corporation - August 2015 Rev. C Page 1 FTLX1471D3BCV Datacom SFP+ Product Specification I. Pin Descriptions Pin Symbol Name/Description Ref. 1 VEET Transmitter Ground 1 2 TFAULT Transmitter Fault 2 3 TDIS Transmitter Disable. Laser output disabled on high or open. 3 4 SDA 2-wire Serial Interface Data Line 4 5 SCL 2-wire Serial Interface Clock Line 4 6 MOD ABS Module Absent. Grounded within the module 4 7 RS0 RS0 for Rate Select: Open or Low = Module supports 1.25 Gb/s 5 High = Module supports 9.95 Gb/s to 10.3125 Gb/s 8 RX LOS Loss of Signal indication. Logic 0 indicates normal operation. 6 9 RS1 No connection required 10 V Receiver Ground 1 EER 11 V Receiver Ground 1 EER 12 RD- Receiver Inverted DATA out. AC Coupled. 13 RD+ Receiver Non-inverted DATA out. AC Coupled. 14 V Receiver Ground 1 EER 15 V Receiver Power Supply CCR 16 V Transmitter Power Supply CCT 17 V Transmitter Ground 1 EET 18 TD+ Transmitter Non-Inverted DATA in. AC Coupled. 19 TD- Transmitter Inverted DATA in. AC Coupled. 20 V Transmitter Ground 1 EET Notes: 1. Circuit ground is internally isolated from chassis ground. 2. T is an open collector/drain output, which should be pulled up with a 4.7k 10k Ohms resistor on the host board if FAULT intended for use. Pull up voltage should be between 2.0V to Vcc + 0.3V. A high output indicates a transmitter fault caused by either the TX bias current or the TX output power exceeding the preset alarm thresholds. A low output indicates normal operation. In the low state, the output is pulled to <0.8V. 3. Laser output disabled on T >2.0V or open, enabled on T <0.8V. DIS DIS 4. Internally pulled down per SFF-8431 Rev 3.0. 5. Transceiver data rate selected through the 2-wire bus in accordance with SFF-8472 Rev. 10.3. Soft RS0 is set at Bit3, Byte 110, Address A2h. Soft RS0 default state on power up is 0 LOW, and the state is reset following a power cycle. Writing 1 HIGH selects max. data rate operation. Transceiver data rate is the logic OR of the input state of the RS0 pin and soft RS0 bit. Thus, if either the RS0 pin OR the soft RS0 bit is HIGH then the selected data rate will be 9.95 and 10.3 Gb/s. Conversely, to select data rate 1.25 Gb/s both the RS0 pin and the soft RS0 bit are set LOW. 6. LOS is open collector output. Should be pulled up with 4.7k 10k on host board to a voltage between 2.0V and 3.6V. Logic 0 indicates normal operation logic 1 indicates loss of signal. VeeT 20 1 VeeT TD- 19 2 TX Fault TD+ 18 3 TX Disable VeeT 17 4 SDA VccT 16 5 SCL Towards Towards VccR 15 Bezel 6 MOD ABS ASIC VeeR 14 7 RS0 RD+ 13 8 RX LOS RD- 12 9 RS1 VeeR 11 10 VeeR Figure 1. Diagram of Host Board Connector Block Pin Numbers and Names. Finisar Corporation - August 2015 Rev. C Page 2

HS Compliance

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:

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