FUJITSU SEMICONDUCTOR DATA SHEET DS501-00021-2v0-E Memory FRAM 256 K (32 K 8) Bit SPI MB85RS256B DESCRIPTION MB85RS256B is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 32,768 words 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. MB85RS256B adopts the Serial Peripheral Interface (SPI). The MB85RS256B is able to retain data without using a back-up battery, as is needed for SRAM. 12 The memory cells used in the MB85RS256B can be used for 10 read/write operations, which is a significant 2 improvement over the number of read and write operations supported by Flash memory and E PROM. 2 MB85RS256B does not take long time to write data like Flash memories or E PROM, and MB85RS256B takes no wait time. FEATURES Bit configuration : 32,768 words 8 bits Serial Peripheral Interface : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1) Operating frequency : All commands except READ 33 MHz (Max) READ command 25 MHz (Max) 12 High endurance : 10 times / byte Data retention : 10 years ( + 85 C), 95 years ( + 55 C), over 200 years ( + 35 C) Operating power supply voltage : 2.7 V to 3.6 V Low power consumption : Operating power supply current 6 mA (Typ 33 MHz) Standby current 9 A (Typ) Operation ambient temperature range : -40 C to +85 C Package : 8-pin plastic SOP (FPT-8P-M02) RoHS compliant Copyright2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2013.2MB85RS256B PIN ASSIGNMENT (TOP VIEW) CS 1 8 VDD 2 7 SO HOLD WP 3 6 SCK GNDS4 5I (FPT-8P-M02) PIN FUNCTIONAL DESCRIPTIONS Pin No. Pin Name Functional description Chip Select pin This is an input pin to make chips select. When CS is H level, device is in deselect 1CS (standby) status and SO becomes High-Z. Inputs from other pins are ignored for this time. When CS is L level, device is in select (active) status. CS has to be L level before inputting op-code. Write Protect pin This is a pin to control writing to a status register. The writing of status register (see 3WP STATUS REGISTER) is protected in related with WP and WPEN. See WRITING PROTECT for detail. Hold pin This pin is used to interrupt serial input/output without making chips deselect. When 7HOLD HOLD is L level, hold operation is activated, SO becomes High-Z, SCK and SI become do not care. While the hold operation, CS has to be retained L level. Serial Clock pin 6SCK This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. Serial Data Input pin 5SI This is an input pin of serial data. This inputs op-code, address, and writing data. Serial Data Output pin 2SO This is an output pin of serial data. Reading data of FRAM memory cell array and status register data are output. This is High-Z during standby. 8 VDD Supply Voltage pin 4 GND Ground pin 2 DS501-00021-2v0-E