FUJITSU SEMICONDUCTOR MEMORY SOLUTION DATA SHEET DS501-00048-6v1-E Memory FRAM 128K (16K 8) Bit SPI MB85RS128TY(AEC-Q100 Compliant) DESCRIPTION MB85RS128TY is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 16,384 words 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. This product is specifically targeted for high-temperature environment such as automotive applications. MB85RS128TY adopts the Serial Peripheral Interface (SPI). The MB85RS128TY is able to retain data without using a back-up battery, as is needed for SRAM. 13 The memory cells used in the MB85RS128TY can be used for 10 read/write operations, which is a significant 2 improvement over the number of read and write operations supported by Flash memory and E PROM. As MB85RS128TY does not need any waiting time in writing process, the write cycle time of MB85RS128TY 2 is much shorter than that of Flash memories or E PROM. FEATURES Bit configuration : 16,384 words 8 bits Serial Peripheral Interface : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1) Operating frequency : 40 MHz (Max) 13 High endurance : 10 times / byte Data retention : 40.2 years (+85 C), 10.9 years (+105 C) 3.38 years (+125 C) or more Under evaluation for more than 3.38 year(+125 C) Operating power supply voltage : 1.8 V to 3.6 V Low power consumption : Operating power supply current 2.5 mA (Max 40 MHz) Standby current 45 A (Max) Sleep current 12 A (Max) Operation ambient temperature range : 40 C to +125 C Package : 8-pin plastic SOP AEC-Q100 Grade 1 compliant RoHS compliant Copyright 2020 FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED 2020.05MB85RS128TY(AEC-Q100 Compliant) PIN ASSIGNMENT (TOP VIEW) 1 8 VDD CS 2 SO 7 HOLD 3 6 SCK WP 4 5 SI VSS (8-pin plastic SOP) PIN FUNCTIONAL DESCRIPTIONS Pin No. Pin Name Functional description Chip Select pin This is an input pin to make chips select. When CS is H level, device is in deselect 1CS (standby) status and SO becomes High-Z. Inputs from other pins are ignored for this time. When CS is L level, device is in select (active) status. CS has to be L level before inputting op-code. The Chip Select pin is pulled up internally to the VDD pin. Write Protect pin This is a pin to control writing to a status register. The writing of status register (see 3WP STATUS REGISTER) is protected in related with WP and WPEN. See WRITING PROTECT for detail. Hold pin This pin is used to interrupt serial input/output without making chips deselect. When 7HOLD HOLD is L level, hold operation is activated, SO becomes High-Z, SCK and SI become do not care. HOLD OPERATION for detail. Serial Clock pin 6SCK This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. Serial Data Input pin 5SI This is an input pin of serial data. This inputs op-code, address, and writing data. Serial Data Output pin 2SO This is an output pin of serial data. Reading data of FRAM memory cell array and status register data are output. This is High-Z during standby. 8 VDD Supply Voltage pin 4 VSS Ground pin 2 DS501-00048-6v1-E