16 Mbit (x8/x16) Concurrent SuperFlash GLS36VF1601G / GLS36VF1602G GLS36VF1601E / 1602E16Mb (x8/x16) Concurrent SuperFlash Data Sheet FEATURES: Organized as 1M x16 or 2M x8 Erase-Suspend / Erase-Resume Capabilities Dual Bank Architecture for Concurrent Security ID Feature Read/Write Operation Greenliant: 128 bits 16 Mbit Bottom Sector Protection User: 256 Byte - GLS36VF1601G: 4 Mbit + 12 Mbit Fast Read Access Time 16 Mbit Top Sector Protection 70 ns - GLS36VF1602G: 12 Mbit + 4 Mbit Latched Address and Data Single 2.7-3.6V for Read and Write Operations Fast Erase and Program (typical): Superior Reliability Sector-Erase Time: 18 ms Endurance: 100,000 cycles (typical) Block-Erase Time: 18 ms Greater than 100 years Data Retention Chip-Erase Time: 35 ms Low Power Consumption: Program Time: 7 s Active Current: 6 mA typical Automatic Write Timing Standby Current: 4 A typical Internal V Generation PP Auto Low Power Mode: 4 A typical End-of-Write Detection Hardware Sector Protection/WP Input Pin Toggle Bit Protects the 4 outermost sectors (8 KWord) Data Polling in the smaller bank by driving WP low and Ready/Busy pin unprotects by driving WP high CMOS I/O Compatibility Hardware Reset Pin (RST ) Conforms to Common Flash Memory Interface (CFI) Resets the internal state machine to reading JEDEC Standards array data Flash EEPROM Pinouts and command sets Byte Pin Packages Available Selects 8-bit or 16-bit mode 48-ball TFBGA (6mm x 8mm) Sector-Erase Capability 48-lead TSOP (12mm x 20mm) Uniform 2 KWord sectors 56-ball LFBGA (8mm x 10mm) Chip-Erase Capability All non-Pb (lead-free) devices are RoHS compliant Block-Erase Capability Uniform 32 KWord blocks PRODUCT DESCRIPTION The GLS36VF1601G and GLS36VF1602G are 1M x16 or ware Data Protection schemes. Designed, manufactured, 2M x8 CMOS Concurrent Read/Write Flash Memory man- and tested for a wide spectrum of applications, these ufactured with high performance SuperFlash memory tech- devices are offered with a guaranteed endurance of 10,000 nology. The split-gate cell design and thick oxide tunneling cycles. Data retention is rated at greater than 100 years. injector attain better reliability and manufacturability com- These devices are suited for applications that require con- pared with alternate approaches. The devices write (Pro- venient and economical updating of program, configura- gram or Erase) with a 2.7-3.6V power supply and conform tion, or data memory. For all system applications, the to JEDEC standard pinouts for x8/x16 memories. GLS36VF160xG significantly improve performance and Featuring high performance Program, the GLS36VF160xG reliability, while lowering power consumption. These provide a typical Program time of 7 sec and use Toggle devices inherently use less energy during Erase and Pro- Bit, Data Polling, or RY/BY to detect the completion of gram than alternative flash technologies, because the total the Program or Erase operation. To protect against inad- energy consumed is a function of the applied voltage, cur- vertent write, the devices have on-chip hardware and Soft- rent, and time of application. For any given voltage range, 2010 Greenliant Systems, Ltd. www.greenliant.com S71342-03-000 05/1016 Mbit Concurrent SuperFlash GLS36VF1601G / GLS36VF1602G Data Sheet the SuperFlash technology uses less current to program TABLE 1: Concurrent Read/Write State and has a shorter erase time therefore, the total energy Bank 1 Bank 2 consumed during any Erase or Program operation is less No Operation Read than alternative flash technologies. No Operation Write SuperFlash technology provides fixed Erase and Program Note: For the purposes of this table, write means to perform Block- times, independent of the number of Erase/Program or Sector-Erase or Program operations as applicable to the cycles that have occurred. Therefore the system software appropriate bank. or hardware does not have to be modified or de-rated as is The Read operation of the GLS36VF160xG is controlled necessary with alternative flash technologies, whose by CE and OE , both of which have to be low for the Erase and Program times increase with accumulated system to obtain data from the outputs. CE is used for Erase/Program cycles. device selection. When CE is high, the chip is deselected and only standby power is consumed. OE is the output To meet high-density, surface-mount requirements, the control and is used to gate data from the output pins. The GLS36VF1601G and GLS36VF1602G devices are offered data bus is in a high impedance state when either CE or in 48-ball TFBGA, 48-lead TSOP, and 56-ball LFBGA OE is high. Refer to Figure 9, the Read cycle timing dia- packages. See Figures 6, 7, and 8 for pin assignments. gram, for further details. Device Operation Program Operation Memory operation functions are initiated using standard These devices are programmed on a word-by-word or microprocessor write sequences. A command is written by byte-by-byte basis depending on the state of the BYTE asserting WE low while keeping CE low. The address pin. Before programming, ensure that the sector which is bus is latched on the falling edge of WE or CE , which- being programmed is fully erased. ever occurs last. The data bus is latched on the rising edge of WE or CE , whichever occurs first. The Program operation is accomplished in three steps: 1. Initiate Software Data Protection using the three- Auto Low Power Mode byte load sequence. These devices also have the Auto Lower Power mode 2. Load address and data. which puts them in a near-standby mode within 500 ns During the Program operation, the addresses are after data has been accessed with a valid Read operation. latched on the falling edge of either CE or WE , This reduces the typical I active Read current to 4 A. DD whichever occurs last. The data is latched on the While CE is low, the devices exit Auto Low Power mode rising edge of either CE or WE , whichever with any address transition or control signal transition used occurs first. to initiate another Read cycle, with no access time penalty. 3. Initiate the internal Program operation after the ris- ing edge of the fourth WE or CE , whichever Concurrent Read/Write Operation occurs first. The Program operation, once initi- The dual bank architecture of these devices allows the ated, will be completed typically within 7 s. Concurrent Read/Write operation whereby the user can See Figures 10 and 11 for WE and CE controlled Pro- read from one bank while programming or erasing in the gram operation timing diagrams and Figure 25 for flow- other bank. For example, reading system code in one bank charts. During the Program operation, the only valid reads while updating data in the other bank. See Table 1 below are Data Polling and Toggle Bit. During the internal Pro- for more information. gram operation, the host is free to perform additional tasks. Any commands issued during an internal Program opera- TABLE 1: Concurrent Read/Write State tion are ignored. Bank 1 Bank 2 Read No Operation Read Write Write Read Write No Operation 2010 Greenliant Systems, Ltd. S71342-03-000 05/10 2