Product Information

GS74117AGX-12I

GS74117AGX-12I electronic component of GSI Technology

Datasheet
SRAM 3.3V 256K x 16 4M I Temp

Manufacturer: GSI Technology
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

135: USD 7.5812 ea
Line Total: USD 1023.46

0 - Global Stock
MOQ: 135  Multiples: 135
Pack Size: 135
Availability Price Quantity
0 - WHS 1


Ships to you between Mon. 27 May to Wed. 29 May

MOQ : 135
Multiples : 135

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GS74117AGX-12I
GSI Technology

135 : USD 7.5019
270 : USD 7.4902

     
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GS74117AX 8, 10, 12 ns FP-BGA 256K x 16 3.3 V V DD Commercial Temp Center V and V DD SS 4Mb Asynchronous SRAM Industrial Temp Features Fine Pitch BGA 256K x 16 Bump Configuration Fast access time: 8, 10, 12 ns 1 2 3 4 5 6 CMOS low power operation: 130/105/95 mA at minimum cycle time Single 3.3 V power supply LB OE A0 A1 A2 NC A All inputs and outputs are TTL-compatible Byte control B DQ1 UB A3 A4 CE DQ16 Fully static operation Industrial Temperature Option: 40 to 85C C DQ3 DQ2 A5 A6 DQ15 DQ14 Package: D VSS DQ4 A17 A7 DQ13 VDD X: 6 mm x 10 mm Fine Pitch Ball Grid Array package GX: Pb-Free 6 mm x 10 mm Fine Pitch Ball Grid Array E VDD DQ5 NC A16 DQ12 VSS package F DQ6 DQ7 A8 A9 DQ10 DQ11 Description G DQ8 NC A10 A11 WE DQ9 The GS74117A is a high speed CMOS Static RAM organized as 262,144 words by 16 bits. Static design eliminates the need H NC A12 A13 A14 A15 NC for external clocks or timing strobes. The GS operates on a single 3.3 V power supply and all inputs and outputs are TTL- compatible. The GS74117A is available in a 6 x 10 mm Fine Package X Pitch BGA package. 6 x 10 mm Substrate Top View Pin Descriptions Symbol Description A0A17 Address input DQ1DQ16 Data input/output CE Chip enable input Lower byte enable input LB (DQ1 to DQ8) Upper byte enable input UB (DQ9 to DQ16) WE Write enable input OE Output enable input V +3.3 V power supply DD V Ground SS NC No connect Rev: 1.05b 6/2010 1/12 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS74117AX Block Diagram A0 Row Memory Array Decoder Address Input Buffer Column Decoder A17 CE WE I/O Buffer Control OE _____ UB DQ1 DQ16 Truth Table CE OE WE LB UB DQ1 to DQ8 DQ9 to DQ16 VDD Current H X X X X Not Selected Not Selected ISB1, ISB2 L L Read Read L L H L H Read High Z H L High Z Read L L Write Write IDD L X L L H Write Not Write, High Z H L Not Write, High Z Write L H H X X High Z High Z L X X H H High Z High Z X: H or L Rev: 1.05b 6/2010 2/12 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory

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