GS8161xxD(GT/D)-xxxV 333 MHz150 MHz 100-Pin TQFP & 165-Bump BGA 1M x 18, 512K x 32, 512K x 36 2.5 V or 3.3 V V Commercial Temp DD 2.5 V or 3.3 V I/O Industrial Temp 18Mb Sync Burst SRAMs Linear Burst Order (LBO) input. The Burst function need not Features be used. New addresses can be loaded on every cycle with no IEEE 1149.1 JTAG-compatible Boundary Scan degradation of chip performance. 1.8 V or 2.5 V core power supply 1.8 V or 2.5 V I/O supply Flow Through/Pipeline Reads LBO pin for Linear or Interleaved Burst mode The function of the Data Output register can be controlled by Internal input resistors on mode pins allow floating mode pins the user via the FT mode pin (Pin 14). Holding the FT mode Byte Write (BW) and/or Global Write (GW) operation pin low places the RAM in Flow Through mode, causing Internal self-timed write cycle output data to bypass the Data Output Register. Holding FT Automatic power-down for portable applications high places the RAM in Pipeline mode, activating the rising- JEDEC-standard 165-bump BGA package edge-triggered Data Output Register. RoHS-compliant 100-pin TQFP and 165-bump BGA packages SCD Pipelined Reads available The GS8161xxD(GT/D)-xxxV is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) Functional Description versions are also available. SCD SRAMs pipeline deselect Applications commands one stage less than read commands. SCD RAMs The GS8161xxD(GT/D)-xxxV is an 18,874,368-bit high begin turning off their outputs immediately after the deselect performance synchronous SRAM with a 2-bit burst address command has been captured in the input registers. counter. Although of a type originally developed for Level 2 Byte Write and Global Write Cache applications supporting high performance CPUs, the Byte write operation is performed by using Byte Write enable device now finds application in synchronous SRAM (BW) input combined with one or more individual byte write applications, ranging from DSP main store to networking chip signals (Bx). In addition, Global Write (GW) is available for set support. writing all bytes at one time, regardless of the Byte Write Controls control inputs. Addresses, data I/Os, chip enable (E1), address burst control Sleep Mode inputs (ADSP, ADSC, ADV) and write control inputs (Bx, Low power (Sleep mode) is attained through the assertion BW, GW) are synchronous and are controlled by a positive- (High) of the ZZ signal, or by stopping the clock (CK). edge-triggered clock input (CK). Output enable (G) and power Memory data is retained during Sleep mode. down control (ZZ) are asynchronous inputs. Burst cycles can Core and Interface Voltages be initiated with either ADSP or ADSC inputs. In Burst mode, The GS8161xxD(GT/D)-xxxV operates on a 1.8 V or 2.5 V subsequent burst addresses are generated internally and are power supply. All inputs are 1.8 V or 2.5 V compatible. controlled by ADV. The burst address counter may be Separate output power (V ) pins are used to decouple configured to count in either linear or interleave order with the DDQ output noise from the internal circuits and are 1.8 V or 2.5 V compatible. Parameter Synopsis -333 -250 -200 -150 Unit t 3.0 3.0 3.0 3.8 ns KQ 3.0 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 305 245 205 175 mA Curr (x32/x36) 360 285 235 195 mA t 5.0 5.5 6.5 7.5 ns KQ Flow 5.0 5.5 6.5 7.5 ns tCycle Through Curr (x18) 235 215 205 190 mA 2-1-1-1 Curr (x32/x36) 265 245 225 205 mA Rev: 1.03b 9/2013 1/35 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8161xxD(GT/D)-xxxV GS816118DT-xxxV 100-Pin TQFP Pinout 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 1M X 18 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQA DQB 12 69 DQA 13 DQB 68 V 14 FT 67 SS NC V 15 66 DD V NC 16 65 DD ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB V V 20 61 DDQ DDQ V V 21 60 SS SS DQA 22 DQB 59 23 DQA DQB 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS V 27 54 V DDQ DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.03b 9/2013 2/35 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see