GS816218/36D(B/D)-400/375/333/250/200/150
119 & 165 BGA 400 MHz150 MHz
1M x 18, 512K x 36
Commercial Temp 2.5 V or 3.3 V V
DD
18Mb S/DCD Sync Burst SRAMs
Industrial Temp
2.5 V or 3.3 V I/O
either linear or interleave order with the Linear Burst Order (LBO)
Features
input. The Burst function need not be used. New addresses can be
FT pin for user-configurable flow through or pipeline operation
Single/Dual Cycle Deselect selectable loaded on every cycle with no degradation of chip performance.
IEEE 1149.1 JTAG-compatible Boundary Scan
Flow Through/Pipeline Reads
ZQ mode pin for user-selectable high/low output drive
The function of the Data Output register can be controlled by the
2.5 V +10%/10% core power supply
user via the FT mode . Holding the FT mode pin low places the
3.3 V +10%/10% core power supply
RAM in Flow Through mode, causing output data to bypass the
2.5 V or 3.3 V I/O supply
Data Output Register. Holding FT high places the RAM in
LBO pin for Linear or Interleaved Burst mode
Pipeline mode, activating the rising-edge-triggered Data Output
Internal input resistors on mode pins allow floating mode pins
Register.
Default to SCD x18/x36 Interleaved Pipeline mode
SCD and DCD Pipelined Reads
Byte Write (BW) and/or Global Write (GW) operation
The GS816218/36D is a SCD (Single Cycle Deselect) and DCD
Internal self-timed write cycle
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
Automatic power-down for portable applications
SRAMs pipeline disable commands to the same degree as read
JEDEC-standard 119-bump and 165-bump BGA packages
commands. SCD SRAMs pipeline deselect commands one stage
RoHS-compliant packages available
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
Functional Description
captured in the input registers. DCD RAMs hold the deselect
Applications
command for one full cycle and then begin turning off their
The GS816218/36D is an 18,874,368-bit high performance
outputs just after the second rising edge of clock. The user may
synchronous SRAM with a 2-bit burst address counter. Although
configure this SRAM for either mode of operation using the SCD
of a type originally developed for Level 2 Cache applications
mode input.
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
Byte Write and Global Write
DSP main store to networking chip set support.
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
Controls
signals (Bx). In addition, Global Write (GW) is available for
Addresses, data I/Os, chip enable (E1), address burst control
writing all bytes at one time, regardless of the Byte Write control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
inputs.
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
FLXDrive
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
The ZQ pin allows selection between high drive strength (ZQ low)
with either ADSP or ADSC inputs. In Burst mode, subsequent
for multi-drop bus applications and normal drive strength (ZQ
burst addresses are generated internally and are controlled by
floating or high) point-to-point applications. See the Output Driver
ADV. The burst address counter may be configured to count in
Characteristics chart for details.
Parameter Synopsis
-400 -375 -333 -250 -200 -150 Unit
t 2.5 2.5 2.5 2.5 3.0 3.8 ns
KQ
2.5 2.66 3.3 4.0 5.0 6.7 ns
Pipeline tCycle
3-1-1-1
Curr (x18) 370 350 310 250 210 185 mA
Curr (x36) 430 410 365 290 240 200 mA
t
4.0 4.2 4.5 5.5 6.5 7.5 ns
KQ
Flow
4.0 4.2 4.5 5.5 6.5 7.5 ns
tCycle
Through
Curr (x18) 275 265 255 220 205 190 mA
2-1-1-1
Curr (x36) 315 300 285 250 225 205 mA
Rev: 1.03b 9/2013 1/39 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see GS816218/36D(B/D)-400/375/333/250/200/150
165-Bump BGAx18 Commom I/OTop View (Package D)
1 2 3 4 5 6 7 8 9 10 11
A NC A E1 BB NC E3 BW ADSC ADV A A A
B NC A E2 NC BA CK GW G ADSP A NC B
C NC NC V V V V V V V NC DQPA C
DDQ SS SS SS SS SS DDQ
D NC DQB V V V V V V V NC DQA D
DDQ DD SS SS SS DD DDQ
E NC DQB V V V V V V V NC DQA E
DDQ DD SS SS SS DD DDQ
F NC DQB V V V V V V V NC DQA F
DDQ DD SS SS SS DD DDQ
G NC DQB V V V V V V V NC DQA G
DDQ DD SS SS SS DD DDQ
H FT MCL NC V V V V V NC ZQ ZZ H
DD SS SS SS DD
J DQB NC V V V V V V V DQA NC J
DDQ DD SS SS SS DD DDQ
K DQB NC V V V V V V V DQA NC K
DDQ DD SS SS SS DD DDQ
L DQB NC V V V V V V V DQA NC L
DDQ DD SS SS SS DD DDQ
M DQB NC V V V V V V V DQA NC M
DDQ DD SS SS SS DD DDQ
N DQPB SCD V V NC A NC V V NC NC N
DDQ SS SS DDQ
P NC NC A A TDI A1 TDO A A A A P
R LBO NC A A TMS A0 TCK A A A A R
11 x 15 Bump BGA13 mm x 15 mm Body1.0 mm Bump Pitch
Rev: 1.03b 9/2013 2/39 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see