GS82582DT19/37GE-450/400/375/333 450 MHz333 MHz 165-Bump BGA TM 288Mb SigmaQuad-II+ 1.8 V V Commercial Temp DD Industrial Temp Burst of 4 SRAM 1.8 V and 1.5 V I/O just one element in a family of low power, low voltage HSTL Features I/O SRAMs designed to operate at the speeds needed to 2.0 clock Latency implement economical high performance networking systems. Simultaneous Read and Write SigmaQuad Interface JEDEC-standard pinout and package Clocking and Addressing Schemes Dual Double Data Rate interface Byte Write controls sampled at data-in time The GS82582DT19/37GE SigmaQuad-II+ SRAMs are Burst of 4 Read and Write synchronous devices. They employ two input register clock Dual-Range On-Die Termination (ODT) on Data (D), Byte inputs, K and K. K and K are independent single-ended clock Write (BW), and Clock (K, K) inputs inputs, not differential inputs to a single differential clock input 1.8 V +100/100 mV core power supply buffer. 1.5 V or 1.8 V HSTL Interface Pipelined read operation Each internal read and write operation in a SigmaQuad-II+ B4 Fully coherent read and write pipelines RAM is four times wider than the device I/O bus. An input ZQ pin for programmable output drive strength data bus de-multiplexer is used to accumulate incoming data Data Valid Pin (QVLD) Support before it is simultaneously written to the memory array. An IEEE 1149.1 JTAG-compliant Boundary Scan output data multiplexer is used to capture the data produced RoHS-compliant 165-bump BGA package from a single memory array read and then route it to the appropriate output drivers as needed. Therefore the address field of a SigmaQuad-II+ B4 RAM is always two address pins SigmaQuad Family Overview less than the advertised index depth (e.g., the 16M x 18 has a The GS82582DT19/37GE are built in compliance with the 4M addressable index). SigmaQuad-II+ SRAM pinout standard for Separate I/O synchronous SRAMs. They are 301,989,888-bit (288Mb) SRAMs. The GS82582DT19/37GE SigmaQuad SRAMs are Parameter Synopsis -450 -400 -375 -333 tKHKH 2.2 ns 2.5 ns 2.86 ns 3.0 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns Rev: 1.03d 2/2020 1/26 2012, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS82582DT19/37GE-450/400/375/333 16M x 18 SigmaQuad-II+ SRAMTop View 1 2 3 4 5 6 7 8 9 10 11 A CQ SA SA W BW1 K SA R SA SA CQ B NC Q9 D9 SA NC K BW0 SA NC NC Q8 C NC NC D10 V SA NC SA V NC Q7 D8 SS SS D NC D11 Q10 V V V V V NC NC D7 SS SS SS SS SS E NC NC Q11 V V V V V NC D6 Q6 DDQ SS SS SS DDQ F NC Q12 D12 V V V V V NC NC Q5 DDQ DD SS DD DDQ G NC D13 Q13 V V V V V NC NC D5 DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J NC NC D14 V V V V V NC Q4 D4 DDQ DD SS DD DDQ K NC NC Q14 V V V V V NC D3 Q3 DDQ DD SS DD DDQ L NC Q15 D15 V V V V V NC NC Q2 DDQ SS SS SS DDQ M NC NC D16 V V V V V NC Q1 D2 SS SS SS SS SS N NC D17 Q16 V SA SA SA V NC NC D1 SS SS P NC NC Q17 SA SA QVLD SA SA NC D0 Q0 R TDO TCK SA SA SA ODT SA SA SA TMS TDI 11 x 15 Bump BGA15 x 17 mm Body1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 2. A7 is the expansion address. Rev: 1.03d 2/2020 2/26 2012, GSI Technology Specifications cited are subject to change without notice. For latest documentation see