GS8321Z18/32/36AD-xxxV 333 MHz150 MHz 165-Bump BGA 36Mb Pipelined and Flow Through 1.8 V or 2.5 V V DD Commercial Temp Synchronous NBT SRAM 1.8 V or 2.5 V I/O Industrial Temp Because it is a synchronous device, address, data inputs, and Features read/ write control inputs are captured on the rising edge of the User-configurable Pipeline and Flow Through mode input clock. Burst order control (LBO) must be tied to a power NBT (No Bus Turn Around) functionality allows zero wait rail for proper operation. Asynchronous inputs include the read-write-read bus utilization Sleep mode enable, ZZ and Output Enable. Output Enable can Fully pin-compatible with both pipelined and flow through be used to override the synchronous control of the output NtRAM, NoBL and ZBT SRAMs drivers and turn the RAM s output drivers off at any time. IEEE 1149.1 JTAG-compatible Boundary Scan Write cycles are internally self-timed and initiated by the rising 1.8 V or 2.5 V core power supply edge of the clock input. This feature eliminates complex off- 1.8 V or 2.5 V I/O supply chip write pulse generation required by asynchronous SRAMs LBO pin for Linear or Interleave Burst mode and simplifies input signal timing. Pin-compatible with 2Mb, 4Mb, 8Mb, and 18Mb devices Byte write operation (9-bit Bytes) The GS8321Z18/32/36AD-xxxV may be configured by the 3 chip enable signals for easy depth expansion user to operate in Pipeline or Flow Through mode. Operating ZZ pin for automatic power-down as a pipelined synchronous device, in addition to the rising- JEDEC-standard 165-bump BGA package edge-triggered registers that capture input signals, the device RoHS-compliant 165-bump BGA package available incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by Functional Description the edge triggered output register during the access cycle and The GS8321Z18/32/36AD-xxxV is a 36Mbit Synchronous then released to the output drivers at the next rising edge of Static SRAM. GSI s NBT SRAMs, like ZBT, NtRAM, NoBL clock. or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus The GS8321Z18/32/36AD-xxxV is implemented with GSI s bandwidth by eliminating the need to insert deselect cycles high performance CMOS technology and is available in when the device is switched from read to write cycles. JEDEC-standard 165-bump FP-BGA package. Parameter Synopsis -333 -250 -200 -150 Unit t 3.0 3.0 3.0 3.8 ns KQ 3.0 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 365 290 250 215 mA Curr (x32/x36) 425 345 290 240 mA t 5.0 5.5 6.5 7.5 ns KQ Flow 5.0 5.5 6.5 7.5 ns tCycle Through Curr (x18) 270 245 210 200 mA 2-1-1-1 Curr (x32/x36) 315 280 250 230 mA Rev: 1.03a 12/2020 1/31 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8321Z18/32/36AD-xxxV 165 Bump BGAx18 Commom I/OTop View (Package D) 1 2 3 4 5 6 7 8 9 10 11 A NC A E1 BB NC E3 CKE ADV A A A A B NC A E2 NC BA CK W G A A NC B C NC NC V V V V V V V NC DQA C DDQ SS SS SS SS SS DDQ D NC DQB V V V V V V V NC DQA D DDQ DD SS SS SS DD DDQ E NC DQB V V V V V V V NC DQA E DDQ DD SS SS SS DD DDQ F NC DQB V V V V V V V NC DQA F DDQ DD SS SS SS DD DDQ G NC DQB V V V V V V V NC DQA G DDQ DD SS SS SS DD DDQ H FT MCH NC V V V V V NC NC ZZ H DD SS SS SS DD J DQB NC V V V V V V V DQA NC J DDQ DD SS SS SS DD DDQ K DQB NC V V V V V V V DQA NC K DDQ DD SS SS SS DD DDQ L DQB NC V V V V V V V DQA NC L DDQ DD SS SS SS DD DDQ M DQB NC V V V V V V V DQA NC M DDQ DD SS SS SS DD DDQ N DQB NC V V NC NC NC V V NC NC N DDQ SS SS DDQ P NC NC A A TDI A1 TDO A A A NC P R LBO A A A TMS A0 TCK A A A A R 11 x 15 Bump BGA13 mm x 15 mm Body1.0 mm Bump Pitch Rev: 1.03a 12/2020 2/31 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see