GS8322Z72(C) 250 MHz133 MHz 209 BGA 36Mb Pipelined and Flow Through 2.5 V or 3.3 V V Commercial Temp DD Synchronous NBT SRAM Industrial Temp 2.5 V or 3.3 V I/O Features Because it is a synchronous device, address, data inputs, and NBT (No Bus Turn Around) functionality allows zero wait read/write control inputs are captured on the rising edge of the Read-Write-Read bus utilization fully pin-compatible with input clock. Burst order control (LBO) must be tied to a power both pipelined and flow through NtRAM, NoBL and rail for proper operation. Asynchronous inputs include the ZBT SRAMs Sleep mode enable (ZZ) and Output Enable. Output Enable can 2.5 V or 3.3 V +10%/10% core power supply be used to override the synchronous control of the output 2.5 V or 3.3 V I/O supply drivers and turn the RAM s output drivers off at any time. User-configurable Pipeline and Flow Through mode Write cycles are internally self-timed and initiated by the rising ZQ mode pin for user-selectable high/low output drive edge of the clock input. This feature eliminates complex off- IEEE 1149.1 JTAG-compatible Boundary Scan chip write pulse generation required by asynchronous SRAMs LBO pin for Linear or Interleave Burst mode and simplifies input signal timing. Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices Byte write operation (9-bit Bytes) The GS8322Z72 may be configured by the user to operate in 3 chip enable signals for easy depth expansion Pipeline or Flow Through mode. Operating as a pipelined ZZ Pin for automatic power-down synchronous device, in addition to the rising-edge-triggered JEDEC-standard 209-Bump BGA package registers that capture input signals, the device incorporates a RoHS-compliant package available rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered Functional Description output register during the access cycle and then released to the The GS8322Z72 is a 36Mbit Synchronous Static SRAM. GSI s output drivers at the next rising edge of clock. NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined The GS8322Z72 is implemented with GSI s high performance read/double late write or flow through read/single late write CMOS technology and is available in a JEDEC-standard 209- SRAMs, allow utilization of all available bus bandwidth by bump BGA package. eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Parameter Synopsis -250 -225 -200 -166 -150 -133 Unit t (x72) 3.0 3.0 3.0 3.5 3.8 4.0 ns KQ Pipeline 4.0 4.4 5.0 6.0 6.7 7.5 ns tCycle 3-1-1-1 Curr (x72) 440 410 370 320 300 265 mA t 6.5 7.0 7.5 8.0 8.5 8.5 ns Flow KQ 6.5 7.0 7.5 8.0 8.5 8.5 ns Through tCycle 2-1-1-1 Curr (x72) 315 295 265 255 240 230 mA Rev: 1.08 10/2014 1/29 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8322Z72(C) GS8322Z72C Pad Out209-Bump BGATop View (Package C) 1 2 3 4 5 6 7 8 9 10 11 A DQG DQG A E2 A ADV A E3 A DQB DQB A B DQG DQG BC BG NC W A BB BF DQB DQB B C DQG DQG BH BD NC E1 NC BE BA DQB DQB C V V D DQG DQG NC NC G NC NC DQB DQB D SS SS V V V V V V V E DQPG DQPC DQPF DQPB E DDQ DDQ DD DD DD DDQ DDQ V V V V V V F DQC DQC ZQ DQF DQF F SS SS SS SS SS SS V V V V V V G DQC DQC MCH DQF DQF G DDQ DDQ DD DD DDQ DDQ V V V V V H DQC DQC MCL V DQF DQF H SS SS SS SS SS SS V V V V V V J DQC DQC MCH DQF DQF J DDQ DDQ DD DD DDQ DDQ V V K NC NC CK NC CKE NC NC NC NC K SS SS V V V V V V L DQH DQH FT DQA DQA L DDQ DDQ DD DD DDQ DDQ V V V V V V M DQH DQH MCL DQA DQA M SS SS SS SS SS SS V V V V V V N DQH DQH MCH DQA DQA N DDQ DDQ DD DD DDQ DDQ V V V V V V P DQH DQH ZZ DQA DQA P SS SS SS SS SS SS V V V V V V V R DQPD DQPH DQPA DQPE R DDQ DDQ DD DD DD DDQ DDQ V V T DQD DQD NC NC LBO NC NC DQE DQE T SS SS U DQD DQD NC A NC A A A NC DQE DQE U V DQD DQD A A A A1 A A A DQE DQE V W DQD DQD TMS TDI A A0 A TDO TCK DQE DQE W 2 11 x 19 Bump BGA14 x 22 mm Body1 mm Bump Pitch Rev: 1.08 10/2014 2/29 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see