GS8342TT06/11/20/38BD-550/500/450/400/350 550 MHz350 MHz 165-Bump BGA TM 36Mb SigmaDDR -II+ 1.8 V V Commercial Temp DD Industrial Temp Burst of 2 SRAM 1.8 V or 1.5 V I/O SRAMs are just one element in a family of low power, low Features voltage HSTL I/O SRAMs designed to operate at the speeds 2.5 Clock Latency needed to implement economical high performance TM Simultaneous Read and Write SigmaDDR Interface networking systems. JEDEC-standard pinout and package Double Data Rate interface Clocking and Addressing Schemes Byte Write controls sampled at data-in time The GS8342TT06/11/20/38BD SigmaDDR-II+ SRAMs are Burst of 2 Read and Write synchronous devices. They employ two input register clock Dual-Range On-Die Termination (ODT) on Data (D), Byte inputs, K and K. K and K are independent single-ended clock Write (BW), and Clock (K, K) inputs inputs, not differential inputs to a single differential clock input 1.8 V +100/100 mV core power supply buffer. 1.5 V or 1.8 V HSTL Interface Pipelined read operation Each internal read and write operation in a SigmaDDR-II+ B2 Fully coherent read and write pipelines RAM is two times wider than the device I/O bus. An input data ZQ pin for programmable output drive strength bus de-multiplexer is used to accumulate incoming data before Data Valid Pin (QVLD) Support it is simultaneously written to the memory array. An output IEEE 1149.1 JTAG-compliant Boundary Scan data multiplexer is used to capture the data produced from a 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package single memory array read and then route it to the appropriate RoHS-compliant 165-bump BGA package available output drivers as needed. Therefore the address field of a SigmaDDR-II+ B2 RAM is always one address pin less than SigmaDDR-II Family Overview the advertised index depth (e.g., the 4M x 8 has a 2M The GS8342TT06/11/20/38BD are built in compliance with addressable index). the SigmaDDR-II+ SRAM pinout standard for Common I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342TT06/11/20/38BD SigmaDDR-II+ Parameter Synopsis -550 -500 -450 -400 -350 tKHKH 1.81 ns 2.0 ns 2.2 ns 2.5 ns 2.86 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns Rev: 1.02b 8/2017 1/30 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8342TT06/11/20/38BD-550/500/450/400/350 1M x 36 SigmaDDR-II+ SRAMTop View 1 2 3 4 5 6 7 8 9 10 11 NC/SA NC/SA A CQ SA R/W BW2 K BW1 LD SA CQ (144Mb) (72Mb) NC/SA B NC DQ27 DQ18 SA BW3 K BW0 SA NC DQ8 (288Mb) C NC NC DQ28 V SA NC SA V NC DQ17 DQ7 SS SS D NC DQ29 DQ19 V V V V V NC NC DQ16 SS SS SS SS SS E NC NC DQ20 V V V V V NC DQ15 DQ6 DDQ SS SS SS DDQ F NC DQ30 DQ21 V V V V V NC NC DQ5 DDQ DD SS DD DDQ G NC DQ31 DQ22 V V V V V NC NC DQ14 DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J NC NC DQ32 V V V V V NC DQ13 DQ4 DDQ DD SS DD DDQ K NC NC DQ23 V V V V V NC DQ12 DQ3 DDQ DD SS DD DDQ L NC DQ33 DQ24 V V V V V NC NC DQ2 DDQ SS SS SS DDQ M NC NC DQ34 V V V V V NC DQ11 DQ1 SS SS SS SS SS N NC DQ35 DQ25 V SA SA SA V NC NC DQ10 SS SS P NC NC DQ26 SA SA QVLD SA SA NC DQ9 DQ0 R TDO TCK SA SA SA ODT SA SA SA TMS TDI 2 11 x 15 Bump BGA13 x 15 mm Body1 mm Bump Pitch Notes: 1. BW0 controls writes to DQ0:DQ8 BW1 controls writes to DQ9:DQ17 BW2 controls writes to DQ18:DQ26 BW3 controls writes to DQ27:DQ35. 2. Pins A2, A10, and B9 are the expansion addresses. Rev: 1.02b 8/2017 2/30 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see