PLDC20RA10 Reprogrammable Asynchronous CMOS Logic Device 1PLDC20RA10 I max = 85 mA (Military) CC High reliability Features Proven EPROM technology Advanced-user programmable macrocell >2001V input protection CMOS EPROM technology for reprogrammability 100% programming and functional testing Up to 20 input terms Windowed DIP, windowed LCC, DIP, LCC, PLCC avail- 10 programmable I/O macrocells able Output macrocell programmable as combinatorial or asynchronous D-type registered output Functional Description Product-term control of register clock, reset and set and output enable The Cypress PLDC20RA10 is a high-performance, sec- ond-generation programmable logic device employing a flexi- Register preload and power-up reset ble macrocell structure that allows any individual output to be Four data product terms per output macrocell configured independently as a combinatorial output or as a Fast fully asynchronous D-type registered output. Commercial The Cypress PLDC20RA10 provides lower-power operation t = 15 ns PD with superior speed performance than functionally equivalent t = 15 ns CO bipolar devices through the use of high-performance 0.8-mi- t = 7 ns SU cron CMOS manufacturing technology. Military The PLDC20RA10 is packaged in a 24 pin 300-mil molded t = 20 ns PD DIP, a 300-mil windowed cerDIP, and a 28-lead square lead- t = 20 ns CO less chip carrier, providing up to 20 inputs and 10 outputs. t = 10 ns SU When the windowed device is exposed to UV light, the 20RA10 Low power is erased and can then be reprogrammed. I max - 80 mA (Commercial) CC Logic Block Diagram V I I I I II II I I PL SS 9 8 7 6 5 4 321 0 12 11 10 98 7 6 5 432 1 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 44 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 13 14 15 16 17 18 19 20 21 22 23 24 OE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O V 9 8 7 6 5 4 3 2 1 0 CC RA101 Cypress Semiconductor Corporation 3901NorthFirstStreet San Jose CA 95134 408-943-2600 Document : 38-03012 Rev. ** Revised March 26, 1997I I I I I I I PLDC20RA10 Selection Guide t ns t ns t ns t ns PD SU CO CC Generic Part Number Coml Mil Coml Mil Coml Mil Coml Mil 20RA10-15 15 7 15 80 20RA10-20 20 20 10 10 20 20 80 85 20RA10-25 25 15 25 85 20RA10-35 35 20 35 85 Pin Configurations 1 LCC STD PLCC/HLCC JEDEC PLCC/HLCC Top View Top View Top View 4 3 2 1 282726 4 3 2 1 2827 26 4 3 2 1 2827 26 I 5 25 NC 2 5 I 6 24 NC 25 I/O I/O 2 5 3 I 25 I/O 2 2 2 I I 7 23 6 24 I/O I/O 3 3 I 6 4 24 I/O 3 3 3 I 7 I 8 22 23 I/O 5 I/O 4 4 I PLDC20RA10 4 7 I/O 4 23 4 8 PLDC20RA10 I 9 NC I/O 21 I/O 22 5 PLDC20RA10 5 8 6 NC 22 NC I I 9 I/O 10 20 I/O 5 21 6 I 6 9 CG7C324 7 5 21 I/O 5 I 11 19 10 I/O 6 20 7 I NC I/O 10 20 I/O 7 6 6 11 19 NC 12131415161718 NC I 11 I/O 19 121314 1516 1718 7 7 121314 1516 1718 RA102 RA103RA104 product terms and four uncommitted product terms of each Macrocell Architecture programmable I/O macrocell that has been configured as an Figure 1 illustrates the architecture of the 20RA10 macrocell. output. The cell dedicates three product terms for fully asynchronous An I/O cell is programmed as an input by tying the output en- control of the register set, reset, and clock functions, as well able pin (pin 13) HIGH or by programming the output enable as, one term for control of the output enable function. product term to provide a LOW, thereby disabling the output The output enable product term output is ANDed with the input buffer, for all possible input combinations. from pin 13 to allow either product term or hardwired external When utilizing the I/O macrocell as an output, the input path control of the output or a combination of control from both functions as a feedback path allowing the output signal to be sources. If product-term-only control is selected, it is automat- fed back as an input to the product term array. When the output ically chosen for all outputs since, for this case, the external cell is configured as a registered output, this feedback path output enable pin must be tied LOW. The active polarity of may be used to feed back the current output state to the device each output may be programmed independently for each out- inputs to provide current state control of the next output state put cell and is subsequently fixed. Figure 2 illustrates the out- as required for state machine implementation. put enable options available. When an I/O cell is configured as an output, combinatorial-only Preload and Power-Up Reset capability may be selected by forcing the set and reset product Functional testability of programmed devices is enhanced by term outputs to be HIGH under all input conditions. This is inclusion of register preload capability, which allows the state achieved by programming all input term programming cells for of each register to be set by loading each register from an these two product terms. Figure 3 illustrates the available out- external source prior to exercising the device. Testing of com- put configuration options. plex state machine designs is simplified by the ability to load An additional four uncommitted product terms are provided in an arbitrary state without cycling through long test vector se- each output macrocell as resources for creation of user-de- quences to reach the desired state. Recovery from illegal fined logic functions. states can be verified by loading illegal states and observing recovery. Preload of a particular register is accomplished by Programmable I/O impressing the desired state on the register output pin and lowering the signal level on the preload control pin (pin1) to a Because any of the ten I/O pins may be selected as an input, logic LOW level. If the specified preload set-up, hold and pulse the device input configuration programmed by the user may width minimums have been observed, the desired state is vary from a total of nine programmable plus ten dedicated in- loaded into the register. To insure predictable system initializa- puts (a total of nineteen inputs) and one output down to a tion, all registers are preset to a logic LOW state upon pow- ten-input, ten-output configuration with all ten programmable er-up, thereby setting the active LOW outputs to a logic HIGH. I/O cells configured as outputs. Each input pin available in a given configuration is available as an input to the four control Note: 1. The CG7C324 is the PLDC20RA10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The principal difference is in the location of the no connect (NC) pins Document : 38-03012 Rev. ** Page 2 of 14 NC 8 I 9 1 V SS I 0 OE PL I/O V 9 CC I/O 8 I/O 0 NC I/O 1 7 I 2 8 I 1 I 9 0 V SS PL V OE CC I/O I/O 9 0 I/O 8 I/O 1 I 1 8 I 9 0 V SS PL NC NC OE V CC I/O 9 I/O 0 I/O 8 I/O 1