Product Information

AM79C973BKCW

AM79C973BKCW electronic component of Infineon

Datasheet
Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 160-Pin PQFP Tray

Manufacturer: Infineon
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Price (USD)

1: USD 49.2011 ea
Line Total: USD 49.2011

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
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0 - Global Stock


Ships to you between Thu. 04 Apr to Wed. 10 Apr

MOQ : 1
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AM79C973BKCW
Infineon

1 : USD 49.2011
10 : USD 39.3608
50 : USD 35.7921
100 : USD 26.2537
500 : USD 24.6005
1000 : USD 23.1572

     
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Rad Hardened
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PRELIMINARY Am79C973/Am79C975 PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY Supports PC98/PC99 and Wired for DISTINCTIVE CHARACTERISTICS Management baseline specifications Single-chip PCI-to-Wire Fast Ethernet controller Full OnNow support including pattern 32-bit glueless PCI host interface matching and link status wake-up events Supports PCI clock frequency from DC to Implements AMDs patented Magic Packet 33 MHz independent of network clock technology for remote wake-up & power-on Supports network operation with PCI clock Magic Packet mode and the physical address from 15 MHz to 33 MHz loaded from EEPROM at power up without requiring PCI clock High performance bus mastering architecture with integrated Direct Memory Supports PCI Bus Power Management Access (DMA) Buffer Management Unit for Interface Specification Revision 1.1 low CPU and bus utilization Supports Advanced Configuration and PCI specification revision 2.2 compliant Power Interface (ACPI) Specification Version 1.0 Supports PCI Subsystem/Subvendor ID/ Vendor ID programming through the Supports Network Device Class Power EEPROM interface Management Specification Version 1.0a Supports both PCI 5.0 V and 3.3 V signaling Serial Management Interface enables remote environments alerting of system management events 2 Plug and Play compatible Inter-IC (I C) compliant electrical interface Big endian and little endian byte alignments System Management Bus (SMBus) supported compliant signaling interface and register access protocol Fully Integrated 10/100 Mbps Physical Layer Interface (PHY) Optional interrupt pin simplifies software interface Conforms to IEEE 802.3 standard for 10BASE-T, 100BASE-TX, and 100BASE-FX Large independent internal TX and RX FIFOs interfaces Programmable FIFO watermarks for both TX Integrated 10BASE-T transceiver with on- and RX operations chip filtering RX frame queuing for high latency PCI bus Fully integrated MLT-3 encoder/decoder for host operation 100BASE-TX Programmable allocation of buffer space Provides a PECL interface for 100BASE-FX between RX and TX queues fiber implementations EEPROM interface supports jumperless design Full-duplex capability for 10BASE-T and and provides through-chip programming 100BASE-TX Supports extensive programmability of IEEE 802.3u Auto-Negotiation between 10 device operation through EEPROM mapping Mbps and 100 Mbps, half- and full-duplex op- Supports up to 1 megabyte (Mbyte) optional eration Boot PROM and Flash for diskless node Dual-speed CSMA/CD (10 Mbps and 100 Mbps) application Media Access Controller (MAC) compliant with Extensive programmable internal/external IEEE/ANSI 802.3 and Blue Book Ethernet loopback capabilities standards Extensive programmable LED status support This document contains information on a product under development at Advanced Micro Devices. The information Publication 21510 Rev: E Amendment/0 is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed Issue Date: August 2000 product without notice. Rf t AMD W b it( d )f thl t t iftiP R E L I M INARY Look-Ahead Packet Processing (LAPP) data mode for board-level production connectivity handling technique reduces system overhead test by allowing protocol analysis to begin before Compatible with the existing PCnet Family the end of a receive frame driver/diagnostic software Includes Programmable Inter Packet Gap (IPG) Software compatible with AMD PCnet Family to address less network aggressive MAC and LANCE/C-LANCE register and controllers descriptor architecture Offers the Modified Back-Off algorithm to Available in 160-pin PQFP and 176-pin TQFP address the Ethernet Capture Effect packages IEEE 1149.1-compliant JTAG Boundary Scan Advanced +3.3 V CMOS process technology for test access port interface and NAND tree test low power operation GENERAL DESCRIPTION The Am79C973 and Am79C975 controllers are single- ler (MAC), a large Transmit FIFO and a large Receive chip 32-bit full- duplex, 10/100-Megabit per second FIFO, and an IEEE 802.3-compliant 10/100 Mbps PHY. (Mbps) fully integrated PCI-to-Wire Fast Ethernet sys- The integrated 10/100 PHY unit of the Am79C973 and tem solution, designed to address high-performance Am79C975 controllers implement the complete physi- system application requirements. They are flexible bus cal layer for 10BASE-T and the Physical Coding Sub- mastering device that can be used in any application, layer (PCS), Physical Medium Attachment (PMA), and including network-ready PCs and bridge/router de- Physical Medium Dependent (PMD) functionality for signs. The bus master architecture provides high data 100BASE-TX, including MLT-3 encoding/decoding. It throughput and low CPU and system bus utilization. also supports 100BASE-FX operation by providing a The Am79C973 and Am79C975 controllers are fabri- Pseudo-ECL (PECL) interface for direct connection to cated with advanced low-power 3.3-V CMOS process a fiber optic transceiver module. The internal 10/100 to provide low operating current for power sensitive ap- PHY implements Auto-Negotiation for twisted-pair plications. (10T/100TX) operation by using a modified 10BASE-T The third generation Am79C973 and Am79C975 Fast link integrity test pulse sequence as defined in the Ethernet controllers also have several enhancements IEEE 802.3u specification. The Auto-Negotiation func- over their predecessors, the Am79C971 and tion automatically configures the controller to operate Am79C972 devices. Besides integrating the complete at the maximum performance level supported across 10/100 Physical Layer (PHY) interface, they further re- the network link. duce system implementation cost by integrating the The Am79C975 controller also implements a Serial SRAM buffers on chip. Management Interface in addition to the advanced The Am79C973 and Am79C975 controllers contain 12- management features offered with the Am79C973 con- kilobyte (Kbyte) buffers, the largest of their class in 10/ troller. The Serial Management Interface is based on 2 100 Mbps Ethernet controllers. The large internal buff- the industry standard Inter-IC (I C) and System Man- ers are fully programmable between the RX and TX agement Bus (SMBus) specifications and enables a queues for optimal performance. system to communicate with another network station for remote monitoring and alerting of local system man- The Am79C973 and Am79C975 controllers are also agement parameters and events. This simple yet pow- compliant with PC98/PC99 and Wired for Management erful Serial Management Interface is capable of specifications. They fully support Microsofts OnNow communicating within the system and over the network and ACPI specifications, which are backward compati- during normal operation or in low-power modes, even if ble with Magic Packet technology and compliant with the device is not initialized or set up for transmit or re- the PCI Bus Power Management Interface Specifica- ceive operation by the network software driver. tion by supporting the four power management states (D0, D1, D2, and D3), the optional PME pin, and the The 32-bit multiplexed bus interface unit provides a di- necessary configuration and data registers. rect interface to the PCI local bus, simplifying the design of an Ethernet node in a PC system. The The Am79C973 and Am79C975 controllers are com- Am79C973 and Am79C975 controllers provide the plete Ethernet nodes integrated into a single VLSI de- complete interface to an Expansion ROM or Flash de- vice. It contains a bus interface unit, a Direct Memory vice allowing add-on card designs with only a single Access (DMA) Buffer Management Unit, an ISO/IEC load per PCI bus interface pin. With their built-in sup- 8802-3 (IEEE 802.3)- compliant Media Access Control- port for both little and big endian byte alignment, the 2 Am79C973/Am79C975

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8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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Cypress / Spansion
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Cypress Semiconductor
Cypress Semiconductor Corp
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INFINEON
Infineon IR
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Infineon (IRF)
Infineon / Cypress
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INFINEON TECH ICs
Infineon Technologies
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Infinite Power Solutions
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International Rectifier HiRel Products
INTL RECTIFIER
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IRH
Ramtron
Ramtron / Cypress Semiconductor
Ramtron International Corp
SP9
SPANSION

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