CY14V101Q3 1 Mbit (128 K 8) Serial SPI nvSRAM Low power consumption Features Core V = 3.0 V to 3.6 V I/O V = 1.65 V to 1.95 V CC CCQ 1-Mbit nonvolatile static random access memory (nvSRAM) Average active current of 10 mA at 30 MHz operation Internally organized as 128 K 8 Industry standard configurations STORE to QuantumTrap nonvolatile elements initiated Industrial temperature automatically on power-down (AutoStore) or by user using 16-pin small outline integrated circuit (SOIC) package HSB pin (Hardware STORE) or SPI instruction (Software Restriction of hazardous substances (RoHS) compliant STORE) RECALL to SRAM initiated on power-up Functional Overview (Power-Up RECALL) or by SPI instruction (Software RECALL) The Cypress CY14V101Q3 combines a 1 Mbit nvSRAM with a Automatic STORE on power-down with a small capacitor nonvolatile element in each memory cell with serial SPI interface. The memory is organized as 128 K words of 8 bits each. The High reliability embedded nonvolatile elements incorporate the QuantumTrap Infinite read, write, and RECALL cycles technology, creating the worlds most reliable nonvolatile 1 million STORE cycles to QuantumTrap memory. The SRAM provides infinite read and write cycles, while Data retention: 20 years the QuantumTrap cell provides highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile High speed serial peripheral interface (SPI) elements (STORE operation) takes place automatically at 30 MHz clock rate power-down. On power-up, data is restored to the SRAM from Supports SPI mode 0 (0,0) and mode 3 (1,1) the nonvolatile memory (RECALL operation). Both STORE and Write protection RECALL operations can also be initiated by the user through SPI instruction. Hardware protection using Write Protect (WP) pin Software protection using Write Disable instruction For a complete list of related documentation, click here. Software block protection for 1/4,1/2, or entire array V V V CC CCQ CAP Logic Block Diagram Quantum Trap Power Control CS 128 K X 8 Instruction decode Write protect WP Control logic SCK STORE/RECALL STORE SRAM ARRAY HSB Control HOLD RECALL 128 K X 8 Instruction D0-D7 register A0-A16 Address Decoder SI Data I/O register SO Status register Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 001-67191 Rev. *E Revised November 13, 2014 CY14V101Q3 Contents Pinouts ..............................................................................3 Memory Access .............................................................. 11 Device Operation ..............................................................4 Read Sequence (READ) instruction .......................... 11 SRAM Write .................................................................4 Write Sequence (WRITE) instruction ........................ 11 SRAM Read ................................................................4 Software STORE (STORE) instruction ...................... 13 STORE Operation .......................................................4 Software RECALL (RECALL) instruction .................. 13 AutoStore Operation ....................................................5 AutoStore Enable (ASENB) instruction ..................... 13 Software STORE Operation ........................................5 AutoStore Disable (ASDISB) instruction ................... 13 Hardware STORE and HSB Pin Operation .................5 HOLD Pin Operation ................................................. 14 RECALL Operation ......................................................5 Best Practices ................................................................. 14 Hardware RECALL (Power-Up) ..................................5 Maximum Ratings ........................................................... 15 Software RECALL .......................................................5 DC Electrical Characteristics ........................................ 15 Disabling and Enabling AutoStore ...............................5 Data Retention and Endurance ..................................... 16 Noise Considerations .......................................................6 Capacitance ....................................................................16 Serial Peripheral Interface ...............................................6 Thermal Resistance ........................................................ 16 SPI Overview ...............................................................6 AC Test Conditions ........................................................ 16 SPI Modes ...................................................................7 AC Switching Characteristics ....................................... 17 SPI Operating Features.................................................... 8 AutoStore or Power-Up RECALL .................................. 18 Power-Up ....................................................................8 Software Controlled STORE and RECALL Cycles ...... 19 Power On Reset ..........................................................8 Hardware STORE Cycle ................................................. 20 Power-Down ................................................................8 Ordering Information ...................................................... 21 Active Power and Standby Power Modes ...................8 Ordering Code Definition ........................................... 21 SPI Functional Description ..............................................8 Package Diagrams .......................................................... 22 Status Register .................................................................9 Acronyms ........................................................................23 Read Status Register (RDSR) Instruction ...................9 Document Conventions ................................................. 23 Write Status Register (WRSR) Instruction ..................9 Units of Measure ....................................................... 23 Write Protection and Block Protection .........................10 Document History Page ................................................ 24 Write Enable (WREN) Instruction ..............................10 Sales, Solutions, and Legal Information ...................... 24 Write Disable (WRDI) Instruction ..............................10 Worldwide Sales and Design Support ....................... 24 Block Protection ........................................................10 Products ....................................................................24 Write Protect (WP) Pin ..............................................11 PSoC Solutions ......................................................... 24 Document : 001-67191 Rev. *E Page 2 of 24