Product Information

CY62138EV30LL-45BVXI

CY62138EV30LL-45BVXI electronic component of Infineon

Datasheet
SRAM 2Mb 3V 45ns 256K x 8 LP SRAM

Manufacturer: Infineon
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 4.9335 ea
Line Total: USD 4.93

931 - Global Stock
Ships to you between
Thu. 02 May to Mon. 06 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
931 - Global Stock


Ships to you between Thu. 02 May to Mon. 06 May

MOQ : 1
Multiples : 1
1 : USD 4.9335
10 : USD 4.5195
100 : USD 4.0595
250 : USD 4.0365
500 : USD 3.8985
960 : USD 3.7605
2880 : USD 3.588
4800 : USD 3.473
9600 : USD 3.404

     
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CY62138EV30 MoBL 2-Mbit (256 K 8) Static RAM 2-Mbit (256 K 8) Static RAM Features Functional Description Very high speed: 45 ns The CY62138EV30 is a high performance CMOS static RAM organized as 256K words by eight bits. This device features Wide voltage range: 2.20 V to 3.60 V advanced circuit design to provide ultra low active current. This Pin compatible with CY62138CV30 is ideal for providing More Battery Life (MoBL ) in portable applications such as cellular telephones. The device also has an Ultra low standby power automatic power down feature that significantly reduces power Typical standby current: 1 A consumption. The device can be put into standby mode reducing Maximum standby current: 7 A power consumption when deselected (CE HIGH). Ultra low active power Writing to the device is accomplished by taking Chip Enable (CE) Typical active current: 2 mA at f = 1 MHz and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O through I/O ) is then written into the location specified on 0 7 Easy memory expansion with CE and OE features the address pins (A through A ). 0 18 Automatic power down when deselected Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable Complementary metal oxide semiconductor (CMOS) for (WE) HIGH. Under these conditions, the contents of the memory optimum speed and power location specified by the address pins appear on the I/O pins. Offered in Pb-free 36-ball ball grid array (BGA) package The eight input and output pins (I/O through I/O ) are placed in 0 7 a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). For a complete list of related documentation, click here. Logic Block Diagram I/O 0 Data in Drivers A I/O 1 0 A 1 A 2 I/O A 2 3 A 4 A 5 I/O A 3 256K x 8 6 A 7 ARRAY A 8 A I/O 9 4 A 10 A 11 I/O 5 I/O 6 POWER COLUMN CE DOWN DECODER I/O WE 7 OE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05577 Rev. *H Revised November 20, 2015 ROW DECODER A 12 A 13 A 14 A 15 A 16 A 17 SENSE AMPS CY62138EV30 MoBL Contents Pin Configuration .............................................................3 Ordering Information ...................................................... 12 Product Portfolio ..............................................................3 Ordering Code Definitions ......................................... 12 Maximum Ratings .............................................................4 Package Diagram ............................................................ 13 Operating Range ...............................................................4 Acronyms ........................................................................14 Electrical Characteristics .................................................4 Document Conventions ................................................. 14 Capacitance ......................................................................5 Units of Measure ....................................................... 14 Thermal Resistance ..........................................................5 Document History Page ................................................. 15 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 17 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 17 Data Retention Waveform ................................................6 Products ....................................................................17 Switching Characteristics ................................................7 PSoC Solutions ...................................................... 17 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 17 Truth Table ......................................................................11 Technical Support ..................................................... 17 Document Number: 38-05577 Rev. *H Page 2 of 17

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory
CYP
Cypress
Cypress / Spansion
CYPRESS SEMI
Cypress Semicon
Cypress Semiconductor
Cypress Semiconductor Corp
INF
INFINEON
Infineon IR
INFINEON (CYPRESS)
Infineon (IRF)
Infineon / Cypress
Infineon / IR
INFINEON TECH ICs
Infineon Technologies
INFINEON TECHNOLOGIES AG
Infineon Technologies Americas Corp.
Infinite Power Solutions
INTERNATIONAL RECTIF
INTERNATIONAL RECTIFIER
International Rectifier HiRel Products
INTL RECTIFIER
IR
IRH
Ramtron
Ramtron / Cypress Semiconductor
Ramtron International Corp
SP9
SPANSION

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