CY7B9910-5SC

CY7B9910 Low Skew Clock Buffer Low Skew Clock Buffer The completely integrated PLL enables zero delay capability. Features External divide capability, combined with the internal PLL, allows distribution of a low frequency clock that is multiplied by virtually All outputs skew < 100 ps typical (250 max) any factor at the clock destination. This facility minimizes clock 15 MHz to 80 MHz output operation distribution difficulty while allowing maximum system clock speed and flexibility. Zero input to output delay For a complete list of related documentation, click here. 50% duty cycle outputs Block Diagram Description Outputs drive 50 terminated lines Low operating current Phase Frequency Detector and Filter 24-pin small-outline integrated circuit (SOIC) package The phase frequency detector and Filter blocks accept inputs from the reference frequency (REF) input and the feedback (FB) Jitter: < 200 ps peak-to-peak, < 25 ps RMS input and generate correction information to control the frequency of the voltage controlled oscillator (VCO). These Functional Description blocks, along with the VCO, form a phase-locked loop (PLL) that tracks the incoming REF signal. The CY7B9910 low skew clock buffer offers low skew system clock distribution. These multiple output clock drivers optimize VCO the timing of high performance computer systems. Each of the The VCO accepts analog control inputs from the PLL filter block eight individual drivers can drive terminated transmission lines and generates a frequency. The operational range of the VCO is with impedances as low as 50 . They deliver minimal and determined by the FS control pin. specified output skews and full swing logic levels (CY7B9910 TTL). Logic Block Diagram TEST FB Voltage Phase Filter Controlled Freq Det Oscillator REF FS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07135 Rev. *M Revised November 24, 2017CY7B9910 Contents Pinouts ..............................................................................3 Package Diagram ............................................................ 11 Pin Definitions ..................................................................3 Acronyms ........................................................................12 Test Mode ..........................................................................3 Document Conventions ................................................. 12 Maximum Ratings .............................................................4 Units of Measure ....................................................... 12 Operating Range ...............................................................4 Document History Page ................................................. 13 Electrical Characteristics .................................................4 Sales, Solutions, and Legal Information ...................... 14 Capacitance ......................................................................6 Worldwide Sales and Design Support ....................... 14 Thermal Resistance ..........................................................6 Products ....................................................................14 AC Test Loads and Waveforms .......................................6 PSoCSolutions .......................................................14 Switching Characteristics ................................................7 Cypress Developer Community ................................. 14 AC Timing Diagrams ........................................................8 Technical Support ..................................................... 14 Operational Mode Descriptions ......................................9 Ordering Information ......................................................10 Ordering Code Definitions .........................................10 Document Number: 38-07135 Rev. *M Page 2 of 14