CY7C1010DV33-10VXI

CY7C1010DV33 2-Mbit (256 K 8) Static RAM 2-Mbit (256 K 8) Static RAM Features Functional Description Pin and function compatible with CY7C1010CV33 The CY7C1010DV33 is a high performance CMOS Static RAM organized as 256 K words by 8 bits. Easy memory expansion is High speed provided by an active LOW Chip Enable (CE), an active LOW t = 10 ns AA Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Low active power Enable (WE) inputs LOW. Data on the eight I/O pins (I/O 0 I = 90 mA at 10 ns CC through I/O ) is then written into the location specified on the 7 Low CMOS standby power address pins (A through A ). 0 17 I = 10 mA SB2 Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable 2.0 V data retention (WE) HIGH. Under these conditions, the contents of the memory Automatic power down when deselected location specified by the address pins will appear on the I/O pins. The eight input and output pins (I/O through I/O ) are placed in TTL-compatible inputs and outputs 0 7 a high impedance state when the device is deselected (CE Easy memory expansion with CE and OE features HIGH), the outputs are disabled (OE HIGH), or during a Write operation (CE LOW, and WE LOW). Available in Pb-free 36-pin SOJ and 44-pin TSOP II packages The CY7C1010DV33 is available in 36-pin SOJ and 44-pin TSOP II packages with center power and ground (revolutionary) pinout. For a complete list of related documentation, click here. Logic Block Diagram IO INPUT BUFFER 0 A 0 IO A 1 1 A 2 IO A 2 3 A 4 256K x 8 IO A 3 5 A 6 ARRAY IO A 4 7 A 8 IO A 5 9 A 10 IO 6 CE POWER IO 7 COLUMN DECODER WE DOWN OE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-00062 Rev. *F Revised November 19, 2014 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 SENSE AMPSCY7C1010DV33 Contents Selection Guide ................................................................3 Ordering Information ...................................................... 11 Pin Configuration .............................................................3 Ordering Code Definitions ......................................... 11 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 12 Operating Range ...............................................................4 Acronyms ........................................................................14 Electrical Characteristics .................................................4 Document Conventions ................................................. 14 Capacitance ......................................................................5 Units of Measure ....................................................... 14 Thermal Resistance ..........................................................5 Document History Page ................................................. 15 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 16 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 16 Data Retention Waveform ................................................6 Products ....................................................................16 AC Switching Characteristics .........................................7 PSoC Solutions ...................................................... 16 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 16 Truth Table ......................................................................10 Technical Support ..................................................... 16 Document Number: 001-00062 Rev. *F Page 2 of 16