CY7C372i
UltraLogic 64-Macrocell Flash CPLD
Features Functional Description
64 macrocells in four logic blocks The CY7C372i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
32 I/O pins
FLASH370i family of high-density, high-speed CPLDs. Like
Five dedicated inputs including two clock pins
all members of the FLASH370i family, the CY7C372i is
designed to bring the ease of use and high performance of the
In-System Reprogrammable (ISR) Flash technology
22V10, as well as PCI Local Bus Specification support, to
JTAG interface
high-density CPLDs.
Bus Hold capabilities on all I/Os and dedicated inputs
Like all of the UltraLogic FLASH370i devices, the CY7C372i
No hidden delays is electrically erasable and ISR, which simplifies both design
and manufacturing flows, thereby reducing costs. The
High speed
Cypress ISR function is implemented through a JTAG serial
f = 125 MHz
MAX interface. Data is shifted in and out through the SDI and SDO
pins. The ISR interface is enabled using the programming
t = 10 ns
PD
voltage pin (ISR ). Additionally, because of the superior
EN
t = 5.5 ns
S
routability of the FLASH370i devices, ISR often allows users to
t = 6.5 ns change existing logic designs while simultaneously fixing
CO
pinout assignments.
Fully PCI compliant
The 64 macrocells in the CY7C372i are divided between four
3.3V or 5.0V I/O operation
logic blocks. Each logic block includes 16 macrocells, a
Available in 44-pin PLCC, TQFP, and CLCC packages
72 x 86 product term array, and an intelligent product term
allocator.
Pin-compatible with the CY7C371i
The logic blocks in the FLASH370i architecture are connected
with an extremely fast and predictable routing resourcethe
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Logic Block Diagram CLOCK
INPUTS
INPUTS
3 2
INPUT/CLOCK
INPUT
MACROCELLS
MACROCELLS
2 2
8 I/Os 8 I/Os
LOGIC
LOGIC
I/O -I/O 36 36
BLOCK
0 7 I/O -I/O
BLOCK PIM
24 31
D
A
16 16
8 I/Os 8 I/Os
LOGIC LOGIC
I/O -I/O
36 36
8 15
I/O -I/O
BLOCK BLOCK
16 23
B C
16
16
16
16
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134 408-943-2600
Document #: 38-03033 Rev. *A Revised April 16, 2004
CY7C372i
Selection Guide
7C372i-125 7C372i-100 7C372i-83 7C372iL-83 7C372i-66 7C372iL-66
[1]
Maximum Propagation Delay , t (ns) 10 12 15 15 20 20
PD
Minimum Set-up, t (ns) 5.5 6.0 8 8 10 10
S
[1]
Maximum Clock to Output , t (ns) 6.5 6.5 8 8 10 10
CO
Typical Supply Current, I (mA) 75757545 75 45
CC
Pin Configurations
PLCC
CLCC
TopView
TopView
6 5 4 3 2 1 4443424140
6534 2 1 44 43 42 41 40
I/O /SCLK
5 I/O /SDI
7 39
39 I/O /SDI 27
27
I/O /SCLK 7
5
I/O
I/O 6 8 38 I/O
38 26
26
I/O
6 8
I/O
I/O 7 I/O
9 37
37 25 25
I/O 9
7
I/O
I
36 24 0 10 36 I/O
24
I 10
0
ISR
35 CLK /I CLK /I
1 4 EN 11 35 1 4
ISR
EN 11
GND
34 GND
GND
12 34
GND 12
I
33 3 CLK /I
0 1 13 33 I
3
CLK /I
0 1 13
32 I
2 I/O
8
I/O 14 32 I
2
8 14
31 I/O
23
I/O
9 15 31 I/O
I/O 23
9 15
I/O
30 22
I/O
I/O 16 10 16 30 I/O
10 22
29 I/O
21
I/O
I/O 11 17 29 I/O
11 17 21
18 19 20 21 22 23 24 25 26 27 28
18 19 20 21 22 23 24 25 26 27 28
Note:
1. The 3.3V I/O mode timing adder, t , must be added to this specification when V = 3.3V.
3.3IO CCIO
Document #: 38-03033 Rev. *A Page 2 of 13
I/O
12
I/O
4
I/O /SMODE
13 I/O
3
I/O
14
I/O
2
I/O
15
I/O
V 1
CCINT
I/O
0
GND
GND
I/O
16
V
CCIO
I/O
17
I/O
31
I/O
18
I/O
30
I/O /SDO
19
I/O
29
I/O
20
I/O
28
I/O
12
I/O
4
/SMODE
I/O
I/O
13
3
I/O
14 I/O
2
I/O
15 I/O
1
V
CC I/O
0
GND GND
I/O
16 V
CC
I/O
17 I/O
31
I/O
I/O
18
30
I/O /SDO
I/O
19 29
I/O I/O
28
20