CY7C4265
16 K 18 Deep Sync FIFOs
16 K 18 Deep Sync FIFOs
Features Functional Description
The CY7C4265 are high speed, low power, first-in first-out
High speed, low power, first-in first-out (FIFO) memories
(FIFO) memories with clocked read and write interfaces. All are
16 K 18 (CY7C4265)
18 bits wide and are pin/functionally compatible to the
CY7C42X5 Synchronous FIFO family. The CY7C4265 can be
0.5 micron CMOS for optimum speed and power
cascaded to increase FIFO depth. Programmable features
High speed 100 MHz operation (10 ns read/write cycle times)
include Almost Full/Almost Empty flags. These FIFOs provide
Low power I = 45 mA
solutions for a wide variety of data buffering needs, including high speed
CC
data acquisition, multiprocessor interfaces, and communications
Fully asynchronous and simultaneous read and write operation
buffering.
Empty, full, half full, and programmable almost empty and
These FIFOs have 18-bit input and output ports that are
almost full status flags
controlled by separate clock and enable signals. The input port
TTL compatible
is controlled by a free running Clock (WCLK) and a Write Enable
pin (WEN). When WEN is asserted, data is written into the FIFO on the
Retransmit function
rising edge of the WCLK signal. While WEN is held active, data is
Output enable (OE) pins
continually written into the FIFO on each cycle. The output port is
controlled in a similar manner by a free-running Read Clock (RCLK) and
Independent read and write enable pins
a Read Enable pin (REN). In addition, the CY7C4265 has an Output
Center power and ground pins for reduced noise
Enable pin (OE). The read and write clocks may be tied together for
single-clock operation or the two clocks may be run independently for
Supports free-running 50 percent duty cycle clock inputs
asynchronous read/write applications. Clock frequencies up to 100
MHz are achievable.
Width and depth expansion capability
Retransmit and Synchronous Almost Full/Almost Empty flag
64-pin TQFP and 64-pin STQFP
features are available on these devices. Depth expansion is
Pb-free packages available
possible using the Cascade Input (WXI, RXI), Cascade Output
(WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are
connected to the WXI and RXI pins of the next device, and the WXO
and RXO pins of the last device should be connected to the WXI and
RXI pins of the first device. The FL pin of the first device is tied to V
SS
and the FL pin of all the remaining devices should be tied to V .
CC
For a complete list of related documentation, click here.
D
017
Logic Block Diagram
INPUT
REGISTER
WCLK WEN
FLAG
PROGRAM
WRITE
REGISTER
CONTROL
FF
EF
FLAG
RAM
PAE
LOGIC
ARRAY
PAF
SMODE
16 Kx 18
WRITE READ
POINTER POINTER
RS
RESET
LOGIC
FL/RT
THREESTATE
READ
WXI
OUTPUT REGISTER
EXPANSION
CONTROL
WXO/HF
LOGIC
RXI
OE
Q
RXO 017
RCLK
REN
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-06004 Rev. *J Revised November 20, 2014 CY7C4265
Contents
Pin Configurations ...........................................................3 Width Expansion Configuration .................................... 18
Pin Description .................................................................3 Depth Expansion Configuration
Selection Guide ................................................................3 (with Programmable Flags) ........................................... 18
Density and Package ........................................................4 Ordering Information ...................................................... 21
Pin Definitions ..................................................................4 16 K 18 Deep Sync FIFO ....................................... 21
Maximum Ratings .............................................................5 Ordering Code Definitions ......................................... 21
Operating Range ...............................................................5 Package Diagrams .......................................................... 22
Electrical Characteristics .................................................5 Acronyms ........................................................................24
Capacitance ......................................................................6 Document Conventions ................................................. 24
AC Test Loads and Waveforms .......................................6 Units of Measure ....................................................... 24
Switching Characteristics ................................................7 Document History Page ................................................. 25
Switching Waveforms ......................................................8 Sales, Solutions, and Legal Information ...................... 26
Architecture ....................................................................16 Worldwide Sales and Design Support ....................... 26
Resetting the FIFO ....................................................16 Products ....................................................................26
FIFO Operation .........................................................16 PSoC Solutions ...................................................... 26
Programming .............................................................16 Cypress Developer Community ................................. 26
Flag Operation ...........................................................16 Technical Support ..................................................... 26
Retransmit .......................................................................17
Document Number: 38-06004 Rev. *J Page 2 of 26