CY7C64013C-SXC

CY7C64013C CY7C64113C Full-Speed USB (12-Mbps) Function Full-Speed USB (12-Mbps) Function Features Functional Overview Full-speed USB Microcontroller The CY7C64013C and CY7C64113C are 8-bit One Time Programmable microcontrollers that are designed for full-speed 8-bit USB Optimized Microcontroller USB applications. The instruction set has been optimized Harvard architecture specifically for USB operations, although the microcontrollers 6-MHz external clock source can be used for a variety of non-USB embedded applications. 12-MHz internal CPU clock GPIO 48-MHz internal clock The CY7C64013C features 19 GPIO pins to support USB and Internal memory other applications. The I/O pins are grouped into three ports 256 bytes of RAM (P0 7:0 , P1 2:0 , P2 6:2 , P3 2:0 ) where each port can be 8 KB of PROM (CY7C64013C, CY7C64113C) configured as inputs with internal pull-ups, open drain outputs, or 2 traditional CMOS outputs. There are 16 GPIO pins (Ports 0 and Integrated Master/Slave I C-compatible Controller (100 kHz) 1) which are rated at 7 mA typical sink current. Port 3 pins are enabled through General-Purpose I/O (GPIO) pins rated at 12 mA typical sink current, a current sufficient to drive Hardware Assisted Parallel Interface (HAPI) for data transfer LEDs. Multiple GPIO pins can be connected together to drive a to external devices single output for more drive current capacity. Additionally, each GPIO can be used to generate a GPIO interrupt to the I/O ports microcontroller. All of the GPIO interrupts share the same GPIO Three GPIO ports (Port 0 to 2) capable of sinking 7 mA per interrupt vector. pin (typical) The CY7C64113C has 32 GPIO pins (P0 7:0 , P1 7:0 , P2 7:0 , An additional GPIO port (Port 3) capable of sinking 12 mA per pin (typical) for high current requirements: LEDs P3 7:0 ). Higher current drive achievable by connecting multiple GPIO DAC pins together to drive a common output Each GPIO port can be configured as inputs with internal The CY7C64113C has four programmable sink current I/O pins pull-ups or open drain outputs or traditional CMOS outputs (DAC) pins (P4 7,2:0 ). Every DAC pin includes an integrated A Digital to Analog Conversion (DAC) port with 14-k pull-up resistor. When a 1 is written to a DAC I/O pin, the programmable current sink outputs is available on the output current sink is disabled and the output pin is driven HIGH CY7C64113C devices by the internal pull-up resistor. When a 0 is written to a DAC I/O Maskable interrupts on all I/O pins pin, the internal pull-up resistor is disabled and the output pin provides the programmed amount of sink current. A DAC I/O pin 12-bit free-running timer with one microsecond clock ticks can be used as an input with an internal pull-up by writing a 1 Watchdog Timer (WDT) to the pin. Internal Power-On Reset (POR) The sink current for each DAC I/O pin can be individually programmed to one of 16 values using dedicated Isink registers. USB Specification Compliance DAC bits P4 1:0 can be used as high-current outputs with a Conforms to USB Specification, Version 1.1 programmable sink current range of 3.2 to 16 mA (typical). DAC Conforms to USB HID Specification, Version 1.1 bits P4 7,2 have a programmable current sink range of 0.2 to Supports up to five user configured endpoints 1.0 mA (typical). Multiple DAC pins can be connected together to drive a single output that requires more sink current capacity. Up to four 8-byte data endpoints Each I/O pin can be used to generate a DAC interrupt to the Up to two 32-byte data endpoints microcontroller. Also, the interrupt polarity for each DAC I/O pin Integrated USB transceivers is individually programmable. Improved output drivers to reduce EMI Clock Operating voltage from 4.0 V to 5.5 V DC The microcontroller uses an external 6-MHz crystal and an Operating temperature from 0 to 70 degrees Celsius internal oscillator to provide a reference to an internal PLL-based clock generator. This technology allows the customer application CY7C64013C available in 28-pin SOIC and 28-pin PDIP packages to use an inexpensive 6-MHz fundamental crystal that reduces the clock-related noise emissions (EMI). A PLL clock generator CY7C64113C available in 48-pin SSOP packages provides the 6-, 12-, and 48-MHz clock signals for distribution Industry-standard programmer support within the microcontroller. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-08001 Rev. *D Revised March 8, 2011 + Feedback CY7C64013C CY7C64113C duration of the event in microseconds. The upper four bits of the Memory timer are latched into an internal register when the firmware The CY7C64013C and CY7C64113C have 8 KB of PROM. reads the lower eight bits. A read from the upper four bits actually reads data from the internal register, instead of the timer. This Power on Reset, Watchdog and Free running Time feature eliminates the need for firmware to try to compensate if These parts include power-on reset logic, a Watchdog timer, and the upper four bits increment immediately after the lower eight a 12-bit free-running timer. The power-on reset (POR) logic bits are read. detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at PROM Interrupts address 0x0000. The Watchdog timer is used to ensure the The microcontroller supports 11 maskable interrupts in the microcontroller recovers after a period of inactivity. The firmware vectored interrupt controller. Interrupt sources include the USB may become inactive for a variety of reasons, including errors in Bus Reset interrupt, the 128-s (bit 6) and 1.024-ms (bit 9) the code or a hardware failure such as waiting for an interrupt outputs from the free-running timer, five USB endpoints, the DAC that never occurs. 2 port, the GPIO ports, and the I C-compatible master mode 2 interface. The timer bits cause an interrupt (if enabled) when the I C and HAPI Interface bit toggles from LOW 0 to HIGH 1. The USB endpoints interrupt The microcontroller can communicate with external electronics after the USB host has written data to the endpoint FIFO or after 2 through the GPIO pins. An IC-compatible interface the USB controller sends a packet to the USB host. The DAC accommodates a 100-kHz serial link with an external device. ports have an additional level of masking that allows the user to There is also a Hardware Assisted Parallel Interface (HAPI) select which DAC inputs can cause a DAC interrupt. The GPIO which can be used to transfer data to an external device. ports also have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input Timer transition polarity that causes an interrupt is programmable for each pin of the DAC port. Input transition polarity can be The free-running 12-bit timer clocked at 1 MHz provides two programmed for each GPIO port as part of the port configuration. interrupt sources, 128-s and 1.024-ms. The timer can be used The interrupt polarity can be rising edge (0 to 1) or falling edge to measure the duration of an event under firmware control by (1 to 0). reading the timer at the start of the event and after the event is complete. The difference between the two readings indicates the Document Number: 38-08001 Rev. *D Page 2 of 53 + Feedback