CY8C21234-24SXI

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY8C21634/CY8C21534/CY8C21434 CY8C21334/CY8C21234 PSoC Programmable System-on-Chip PSoC Programmable System-on-Chip Up to eight analog inputs on GPIOs Features Configurable interrupt on all GPIOs Powerful Harvard-architecture processor Versatile analog mux M8C processor speeds up to 24 MHz Common internal analog bus Low power at high speed Simultaneous connection of I/O combinations Operating voltage: 2.4 V to 5.25 V Capacitive sensing application capability Operating voltages down to 1.0 V using on-chip switch mode pump (SMP) Additional system resources 2 2 Industrial temperature range: 40 C to +85 C I C master, slave, and multi-master to 400 kHz Watchdog and sleep timers Advanced peripherals (PSoC blocks) User-configurable low-voltage detection (LVD) Four analog Type E PSoC blocks provide: Integrated supervisory circuit Two comparators with digital-to-analog converter (DAC) On-chip precision voltage reference references Single or dual 10-bit 28 channel analog-to-digital converters (ADC) Logic Block Diagram Four digital PSoC blocks provide: 8- to 32-bit timers, counters, and pulse width modulators (PWMs) Cyclical redundancy check (CRC) and pseudo random sequence (PRS) modules Full-duplex universal asynchronous receiver transmitter (UART), serial peripheral interface (SPI) master or slave Connectable to all general purpose I/O (GPIO) pins Complex peripherals by combining blocks Flexible on-chip memory 8 KB flash program storage 50,000 erase/write cycles 512 bytes static random access memory (SRAM) data storage In-system serial programming (ISSP) Partial flash updates Flexible protection modes EEPROM emulation in flash Complete development tools Free development software (PSoC Designer) Full-featured, in-circuit emulator (ICE) and programmer Full-speed emulation Complex breakpoint structure 128-KB trace memory Precision, programmable clocking 1 Internal 2.5% 24- / 48-MHz main oscillator Internal oscillator for watchdog and sleep Programmable pin configurations 25-mA sink, 10-mA source on all GPIOs Pull-up, pull-down, high Z, strong, or open-drain drive modes on all GPIOs Errata: For information on silicon errata, see Errata on page 50. Details include trigger conditions, devices affected, and proposed workaround. Notes 1. Errata: The worst case IMO frequency deviation when operated below 0 C and above +70 C and within the upper and lower datasheet temperature range is 5%. 2 2 2. Errata: The I C block exhibits occasional data and bus corruption errors when the I C master initiates transactions while the device is transitioning in to or out of sleep mode. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-12025 Rev. AJ Revised July 31, 2019