CY8C29466/CY8C29566 CY8C29666/CY8C29866 PSoC Programmable System-on-Chip PSoC Programmable System-on-Chip Four 40 mA analog outputs on GPIOs Features Configurable interrupt on all GPIOs Powerful Harvard-architecture processor Additional system resources M8C processor speeds to 24 MHz 2 I C slave, master, and multi-master to 400 kHz Two 8 8 multiply, 32-bit accumulate Watchdog and sleep timers Low power at high speed User-configurable low-voltage detection (LVD) Operating voltage: 3.0 V to 5.25 V Integrated supervisory circuit Operating voltages down to 1.0 V using on-chip switch mode On-chip precision voltage reference pump (SMP) Industrial temperature range: 40 C to +85 C Complete development tools Free development software (PSoC Designer) Advanced peripherals (PSoC blocks) Full-featured in-circuit emulator (ICE) and 12 rail-to-rail analog PSoC blocks provide: programmer Up to 14-bit analog-to-digital converters (ADCs) Full-speed emulation Up to 9-bit digital-to-analog converters (DACs) Complex breakpoint structure Programmable gain amplifiers (PGAs) 128 KB trace memory Programmable filters and comparators Complex events 16 digital PSoC blocks provide: C compilers, assembler, and linker 8- to 32-bit timers and counters, 8- and 16-bit pulse-width Logic Block Diagram modulators (PWMs) Cyclical redundancy check (CRC) and pseudo random Port Port Port Port Port Port Port Port 0 with Analog Drivers 7 6 5 4 3 2 1 sequence (PRS) modules PSoC Up to four full-duplex universal asynchronous receiver CORE transmitters (UARTs) System Bus Multiple serial peripheral interface (SPI) masters or slaves Can connect to all general-purpose I/O (GPIO) pins Global Digital Interconnect Global Analog Interconnect Create complex peripherals by combining blocks SRAM SROM Flash 32KB 2KB Precision, programmable clocking 1 Sleep and CPU Core (M8C) Internal 5% 24- / 48-MHz main oscillator Interrupt Watchdog Controller 24- / 48-MHz with optional 32.768 kHz crystal Optional external oscillator, up to 24 MHz Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) Internal oscillator for watchdog and sleep Flexible on-chip memory DIGITAL SYSTEM ANALOG SYSTEM 32 KB flash program storage 50,000 erase/write cycles Analog Ref. 2 KB static random access memory (SRAM) data storage Digital Analog In-system serial programming (ISSP) Block Block Array Array Partial flash updates Analog Input Flexible protection modes Muxing Electrically erasable programmable read-only memory (EEPROM) emulation in flash Programmable pin configurations POR and LVD Internal Switch Digital Multiply 25-mA sink, 10-mA source on all GPIOs 2 Decimator Voltage Mode I C Clocks Accum. System Resets Ref. Pump Pull-up, pull-down, high Z, strong, or open-drain drive modes SYSTEM RESOURCES on all GPIOs Eight standard analog inputs on GPIOs, plus four additional analog inputs with restricted routing Errata: For information on silicon errata, see Errata on page 61. Details include trigger conditions, devices affected, and proposed workaround. Note 1. Errata: When the device is operated within 0 C to 70 C, the frequency tolerance is reduced to 2.5%, but if operated at extreme temperature (below 0 C or above 70 C), frequency tolerance deviates from 2.5% to 5%. For more information, see Errata on page 61. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-12013 Rev. AB Revised August 12, 2015 CY8C29466/CY8C29566 CY8C29666/CY8C29866 Note: For CY8C29X66 devices related Development Kits please More Information click here. Cypress provides a wealth of data at www.cypress.com to help The MiniProg1 and MiniProg3 devices provide interfaces for you to select the right PSoC device for your design, and to help flash programming and debug. you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the PSoC Designer knowledge base article How to Design with PSoC 1, PowerPSoC , and PLC KBA88292. Following is an PSoC Designer is a free Windows-based Integrated Design abbreviated list for PSoC 1: Environment (IDE). Develop your applications using a library of pre-characterized analog and digital peripherals in a Overview: PSoC Portfolio, PSoC Roadmap drag-and-drop design environment. Then, customize your Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP design leveraging the dynamically generated API libraries of code. Figure 1 shows PSoC Designer windows. Note: This is not In addition, PSoC Designer includes a device selection tool. the default view. Application notes: Cypress offers a large number of PSoC 1. Global Resources all device hardware settings. application notes covering a broad range of topics, from basic 2. Parameters the parameters of the currently selected User to advanced level. Recommended application notes for getting Modules. started with PSoC 1 are: 3. Pinout information related to device pins. Getting Started with PSoC 1 AN75320. 4. Chip-Level Editor a diagram of the resources available on PSoC 1 - Getting Started with GPIO AN2094. the selected chip. PSoC 1 Analog Structure and Configuration AN74170. 5. Datasheet the datasheet for the currently selected UM PSoC 1 Switched Capacitor Analog Blocks AN2041. Selecting Analog Ground and Reference AN2219. 6. User Modules all available User Modules for the selected device. Note: For CY8C29X66 devices related Application note please click here. 7. Device Resource Meter device resource usage for the current project configuration. Development Kits: 8. Workspace a tree level diagram of files associated with the CY3210-PSoCEval1 supports all PSoC 1 Mixed-Signal Array project. families, including automotive, except CY8C25/26xxx devices. The kit includes an LCD module, potentiometer, 9. Output output from project build and debug operations. LEDs, and breadboarding space. Note: For detailed information on PSoC Designer, go to CY3214-PSoCEvalUSB features a development board for PSoC Designer > Help > Documentation > the CY8C24x94 PSoC device. Special features of the board Designer Specific Documents > IDE User Guide. include USB and CapSense development and debugging support. Figure 1. PSoC Designer Layout Document Number: 38-12013 Rev. AB Page 2 of 67