CYFB0072V 72-Mbit Video Frame Buffer 72-Mbit Video Frame Buffer Features Functional Description Memory organization The Video Frame Buffer is a 72-Mbit memory device which operates as a FIFO with a bus width of 36 bits. It has independent Density: 72-Mbit read and write ports, which can be clocked up to 133 MHz. The Organization: 36 bus size of 36 bits enables a data throughput of 4.8 Gbps. The 1 Up to 133-MHz clock operation device also offers a simple and easy-to-use interface to reduce implementation and debugging efforts, improve time-to-market, Unidirectional operation and reduce engineering costs. This makes it an ideal memory Independent read and write ports choice for a wide range of applications including video and image processing or any system that needs buffering at high speeds Supports simultaneous read and write operations across different clock domains. Reads and writes operate on independent clocks, upto a maximum ratio of two, enabling data buffering across clock The functionality of the Video Frame Buffer is such that the data domains. is read out of the read port in the same sequence in which it was Supports multiple I/O voltage standard: low voltage written into the write port. If writes and inputs are enabled (WEN complementary metal oxide semiconductor (LVCMOS) 3.3 V & IE), data on the write port gets written into the device at the and 1.8 V voltage standards. rising edge of write clock. Enabling reads and outputs (REN & OE) fetches data on the read port at every rising edge of read Input and output enable control for write mask and read skip clock. Both reads and writes can occur simultaneously at operations different speeds provided the ratio between read and write clock Empty & Full status flags is in the range of 0.5 to 2. Appropriate flags are set whenever the device is empty or full. Flow-through mailbox register to send data from input to output port, bypassing the Frame Buffer The device also supports a flow-through mailbox register to bypass the frame buffer memory Separate serial clock (SCLK) input for serial programming of For a complete list of related documentation, click here. configuration registers Master reset to clear entire Frame Buffer Partial reset to clear data but retain programmable settings Joint test action group (JTAG) port provided for boundary scan function Industrial temperature range: 40 C to +85 C Note 1. For device operating at 150 MHz, Contact Sales. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-88646 Rev. *E Revised November 14, 2017CYFB0072V Logic Block Diagram D 35:0 IE WEN WCLK LD SPI SEN SPI SCLK SPI SI INPUT CONFIGURATION REGISTER REGISTERS/MAILBOX MB WRITE CONTROL LOGIC FF EF WRITE POINTER FLAG LOGIC DVal Memory Array MRS 72-Mbit RESET POINTER PRS READ POINTER TCK TMS JTAG CONTROL READ CONTROL TDO LOGIC TDI OUTPUT RCLK REGISTER REN OE Q 35:0 Document Number: 001-88646 Rev. *E Page 2 of 28