MAX 5000
Programmable Logic
Device Family
June 1996, ver. 3 Data Sheet
n Advanced Multiple Array MatriX (MAX) 5000 architecture
Features...
combining speed and ease-of-use of PAL devices with the density of
programmable gate arrays
n Complete family of high-performance, erasable CMOS EPROM
EPLDs for designs ranging from fast 28-pin address decoders to
100-pin LSI custom peripherals
n 600 to 3,750 usable gates (see Table 1)
n Fast, 15-ns combinatorial delays and 83.3-MHz counter frequencies
n Configurable expander product-term distribution allowing more
than 32 product terms in a single macrocell
n 28 to 100 pins available in DIP, J-lead, PGA, SOIC, and QFP packages
n Programmable registers providing D, T, JK, and SR flipflop
functionality with individual clear, preset, and clock controls
n Programmable security bit for protection of proprietary designs
n Software design support featuring Alteras MAX+PLUS II
development system on 486- or Pentium-based PCs, and
Sun SPARCstation, HP 9000 Series 700, and IBM RISC System/6000
workstations
Table 1. MAX 5000 Device Features
Feature EPM5032 EPM5064 EPM5128 EPM5130 EPM5192
Usable gates 600 1,250 2,500 2,500 3,750
Macrocells 32 64 128 128 192
Logic array blocks (LABs) 1488 12
Expanders 64 128 256 256 384
Routing Global PIA PIA PIA PIA
Maximum user I/O pins 24 36 60 68, 84 72
t (ns) 15 25 25 25 25
PD
t (ns) 44444
ASU
t (ns) 10 14 14 14 14
CO
f (MHz) 76.9 50 50 50 50
CNT
Altera Corporation 311
A-DS-M5000-03
MAX 5000 Programmable Logic Device Family Data Sheet
n Programming support with Alteras Master Programming Unit
...and More
(MPU) or programming hardware from other manufacturers
Features
n Additional design entry and simulation support provided by EDIF,
LPM, Verilog HDL, VHDL, and other interfaces to popular EDA tools
from manufacturers such as Cadence, Data I/O, Exemplar, Mentor
Graphics, MINC, OrCAD, Synopsys, VeriBest, and Viewlogic
The MAX 5000 family combines innovative architecture and advanced
General
process technologies to offer optimum performance, flexibility, and the
Description
highest logic-to-pin ratio of any general-purpose programmable logic
device (PLD) family. The MAX 5000 family provides 600 to 3,750 usable
gates, pin-to-pin delays as fast as 15 ns, and counter frequencies of up to
83.3 MHz. See Table 2.
Table 2. MAX 5000 Timing Parameter Availability
Device Speed (t )
PD1
15 ns 20 ns 25 ns 30 ns 35 ns
EPM5032
vv v
EPM5064
vvv
EPM5128 vvv
EPM5130
vv
EPM5192
vv
The MAX 5000 architecture supports 100% TTL emulation and
high-density integration of multiple SSI, MSI, and LSI logic functions. For
example, an EPM5192 device can replace over 100 74-series devices; it can
integrate complete subsystems into a single package, saving board area
and reducing power consumption. MAX 5000 EPLDs are available in a
wide range of packages (see Table 3), including the following:
n Windowed ceramic and plastic dual in-line (CerDIP and PDIP)
n Windowed ceramic and plastic J-lead chip carrier (JLCC and PLCC)
n Windowed ceramic pin-grid array (PGA)
n Plastic small-outline integrated circuit (SOIC)
n Ceramic and plastic quad flat pack (CQFP and PQFP)
312 Altera Corporation