IR3513ZMTRPBF

NOT RECOMMENDED FOR NEW DESIGNS REPLACEMENT PRODUCT IR3513ZMTRPBF IR3513 DATASHEET TM XPHASE3 POL CONTROL IC DESCRIPTION The IR3513 Control IC provides overall control of a scalable number of phases along with an internal gate driver, current sense/sharing, and PWM. This allows the IR3513 to implement a stand-alone single-phase regulator or interface with additional Phase ICs to develop a power solution with any number of phases. With this arrangement, the final solution requires only 1 IC per phase to deploy 1 to X phases. Other approaches require a control IC plus 1 to X driver ICs or scalable all-in-one ICs that do not utilize all IC pins or circuitry leading to increased solution cost and size. FEATURES 0.8V reference supports 0.8V to 5.1V output voltage with +/-0.5% system set point accuracy Dynamic margin function provides 5 % reference offset 1 (stand-alone) to X phase operation with additional Phase IC Programmable 250 KHz to 9 Mhz daisy-chain digital phase timing provides a per phase switching frequency of 250 KHz to 1.5 MHz with no external components Differential remote sense amplifier with 100kohm input impedance IC bias linear regulator control with programmable output voltage and UVLO Programmable converter current limit during soft-start, hiccup with delay during normal operation Over voltage protection communicated to Phase ICs System over voltage signal protects against failures such as a shorted high side MOSFET Detection and protection of open remote sense lines Open control loop protection 7V/2A gate drivers (4A GATEL sink current) Integrated boot-strap synchronous PFET Small thermally enhanced 32L 5 x 5mm MLPQ package APPLICATION CIRCUIT VIN (8-16V) Optional FUSE ROVP1 RVCCLFB1 RVCCLFB2 SCR CVCCL RVCCLDRV Phase IC ROVP2 CVCC Bias Supply POWER STAGE VIN CIN 1 24 GATEH LGND ROSC CBST 2 23 VOUT+ BOOST ROSC/OVP CSS/DEL CVCCP 3 22 VCCP SS/DEL IR3513 RVREF CVREF COUT 4 21 6 Wire GATEL VREF ROCSET CONTROL 5 20 Control Bus VOUT- PGND OCSET IC to Phase 6 19 LGND IIN ICs 7 18 CSIN+ EAOUT CCS 8 17 RCS CSIN- FB RFB2 CFB CCP RCP ENABLE PG RFB1 CCP1 MARGIN RFB3 ROV2 VOUT REMOTE SENSE - VOUT REMOTE SENSE + Figure 1 - IR3513 Application Circuit Page 1 May 11, 2008 9 32 ENABLE SW 10 31 PG VCC 11 30 MARGIN VCCLDRV 12 29 VOSNS- VVCLFB 13 28 VOSNS+ VCCL 14 27 VCCL PHSIN ROV1 15 26 VOUT PHSOUT 16 25 OVSNS CLKOUTNOT RECOMMENDED FOR NEW DESIGNS REPLACEMENT PRODUCT IR3513ZMTRPBF IR3513 ORDERING INFORMATION Device Package Order Quantity IR3513MTRPBF 32 Lead MLPQ (5 x 5 mm body) 3000 per reel * IR3513MPBF 32 Lead MLPQ(5 x 5 mm body) 100 piece strips Samples only PIN DESCRIPTION PIN PIN SYMBOL PIN DESCRIPTION 1 GATEH High-side driver output and input to GATEL non-overlap comparator. 2 BOOST Supply for high-side driver. An internal bootstrap synchronous PFET is connected between this pin and the VCCP pin. 3 VCCP Supply for low-side driver. An internal bootstrap synchronous PFET is connected from this pin to the BOOST pin. 4 GATEL Low-side driver output and input to GATEH non-overlap comparator. 5 PGND Return for low side driver and reference for GATEH non-overlap comparator. 6, 24 LGND Local Ground for internal circuitry and the IC substrate connection. 7 CSIN+ Non-Inverting input to the current sense amplifier and input to debug comparator. 8 CSIN- Inverting input to the current sense amplifier and input to synchronous rectification disable comparator. 9 ENABLE Enable input. A logic low applied to this pin puts the IC into fault mode. Do not float this pin as the logic state will be undefined. 10 PG Open drain output that drives low during startup and under any external fault condition. Connect external pull-up. 11 MARGIN Tri-state input with internal pull-up to 1.425 V. Low/High voltage shifts the Error Amplifier reference voltage Up/Down 5%. V(MARGIN) should not be biased to a voltage greater than V(VCCL). 12 VOSEN- Inverting remote sense amplifier input. Connect to ground at the load. 13 VOSEN+ Non-inverting remote sense amplifier input. Connect to output at the load. 14, 28 VCCL Output of the voltage regulator, power input for clock oscillator circuitry and other internal circuitry. Connect a decoupling capacitor to LGND. 15 VOUT Remote sense amplifier output. 16 OVSNS Over voltage sense input during normal operation. 17 FB Inverting input to the Error Amplifier. 18 EAOUT Output of the Error Amplifier. 19 IIN Average current input signal from active and inactive phase IC(s). This pin is also used to communicate an over voltage condition to the phase IC(s). 20 OCSET An external resistor tied to VREF along with a fixed internal current source programs the constant output current limit and hiccup over-current thresholds. Over-current protection can be disabled by programming the threshold higher than the possible signal on the IIN pin, but no greater than 5V (do not float this pin). 21 VREF Reference voltage for the Error Amplifier. An external RC network to LGND programs the margin slew rate and compensates the internal buffer amp. 22 SS/DEL An external capacitor to LGND programs converter startup and over current protection delay timing. It is also used to compensate the constant output current loop during soft start. Page 2 May 11, 2008