IR3536/38
Digital Multi-Phase Buck Controller
CHL8326/28
FEATURES DESCRIPTION
6-phase & 8-phase dual output PWM Controller
The IR3536/CHL8326 and IR3538/CHL8328 are dual-loop
digital multi-phase buck controllers. The IR3536/CHL8326
Phases are flexibly assigned between Loops 1 & 2
drive up to 6 phases and the IR3538/CHL8328 drives up to
Intel VR12, AMD 3.4MHz SVI/PVI & Memory
8 phases. The IR3536/CHL8326 and IR3538/CHL8328 are
modes
fully Intel VR12 and AMD SVI/PVI compliant on both
loops and provide a Vtt tracking function for DDR memory.
Overclocking & Gaming Mode with Vmax setting
Switching frequency from 200kHz to 1.2MHz per
The IR3536/CHL8326 and IR3538/CHL8328 include the
phase
IR Efficiency Shaping Technology to deliver exceptional
IR Efficiency Shaping Features including Variable
efficiency at minimum cost across the entire load range.
Gate Drive and Dynamic Phase Control
IR Variable Gate Drive optimizes the MOSFET gate drive
voltage based on real-time load current. IR Dynamic Phase
Programmable 1-phase or 2-phase for Light Loads
Control adds/drops phases based upon load current.
and Active Diode Emulation for Very Light Loads
The IR3536/CHL8326 and IR3538/CHL8328 can be
IR Adaptive Transient Algorithm (ATA) on both loops
configured to enter 1-phase operation and active diode
minimizes output bulk capacitors and system cost
emulation mode automatically or by command.
Auto-Phase Detection with auto-compensation
IRs unique Adaptive Transient Algorithm (ATA), based on
Per-Loop Fault Protection: OVP, UVP, OCP, OTP, CFP
proprietary non-linear digital PWM algorithms, minimizes
I2C/SMBus/PMBus system interface for telemetry
output bulk capacitors.
of Temperature, Voltage, Current & Power for
both loops
The I2C/PMBus interface can communicate with up to 16
Non-Volatile Memory (NVM) for custom
IR3536/CHL8326 and IR3538/CHL8328 based VR loops.
configuration
Device configuration and fault parameters are easily
defined using the IR Intuitive Power Designer (DPDC) GUI
Compatible with IR ATL and 3.3V Tri-state Drivers
and stored in on-chip NVM.
+3.3V supply voltage; -20C to 85C ambient
operation
The IR3536/CHL8326 and IR3538/CHL8328 provides
Pb-Free, RoHS, 7x7 48-pin & 8x8 56-pin QFN, MSL2 extensive OVP, UVP, OCP and OTP fault protection and
package
includes thermistor based temperature sensing with
VR_HOT signal.
APPLICATIONS
NVM storage saves pins and enables a small package size.
The IR3536/CHL8326 and IR3538/CHL8328 also include
Intel VR12 & AMD SVI & PVI based systems
numerous features like register diagnostics for fast design
DDR Memory with Vtt tracking
cycles and platform differentiation, truly simplifying
Overclocked & Gaming platforms VRD design and enabling fastest time-to-market with its
set-and-forget methodology.
PIN DIAGRAM
56 55 54 53 52 51 50 49 48 47 46 45 44 43
48 47 46 45 44 43 42 41 40 39 38 37
ISEN8 1 42 ISEN7
RCSP_L2
RCSP 1 36
RCSP 2 41 RCSP_L2
2 35 RCSM_L2
RCSM RCSM 3 40 RCSM_L2
3 34 VCC 4 39
VCC VCC VCC
1 1
CFP / CFP /
4 33 VSEN_L2 2 5 38 VSEN_L2
2 VFIXEN_PSI
VFIXEN_PSI
6 37
VSEN 5 32 VRTN_L2 VSEN VRTN_L2
CHL8328
CHL8326 VRTN 7 36 PWM8
VRTN 6 31 PWM6
56 Pin 8x8 QFN
48 Pin 7x7 QFN 8 35
RRES PWM7
RRES 7 30 PWM5
Top View
Top View
TSEN 9 34 PWM6
TSEN 8 29 PWM4
V18A 10 33 PWM5
V18A 9 28 PWM3
1
VR_READY /
1 2 11 32 PWM4
VR_READY / PWRGD
PWM2
2 10 27 1
PWRGD VR_READY_L2
2 12 31 PWM3
1 / PWROK
VR_READY_L2
2 11 26 PWM1
/ PWROK
GPO_B 13 30 PWM2
49 GND
57 GND
VINSEN 12 25 VAR_GATE
VINSEN 14 29 PWM1
13 14 15 16 17 18 19 20 21 22 23 24
15 16 17 18 19 20 21 22 23 24 25 26 27 28
1
Intel/MPoL mode
2
AMD mode
Figure 1: IR3536/CHL8326 Package Top View Figure 2: IR3538/CHL8328 Package Top View
1 June 21, 2013 | FINAL | V1.09
1 2
GPO_A / CBOUT IRTN1
1 2
PSI / VID[5] ISEN1
1 2
SV_ALERT / VID[4] IRTN2
1 2
SV_CLK / SVC_VID[3] ISEN2
1 2
SV_DIO / SVD_VID[2] IRTN3
1
VR_HOT# /
2 ISEN3
VRHOT_ICRIT#
ENABLE IRTN4
SMB_ALERT# ISEN4
SMB_DIO IRTN5
SMB_CLK ISEN5
1
SV_ADDR_GPO_D
IRTN6
2
/ VID[1]
1
PM_ADDR_GPO_C /
ISEN6
2
PM_ADDR_VID[0]
1 2
GPO_A / CBOUT IRTN8
1 2
PSI(MPoL) / VID[5] IRTN1
1 2
SV_ALERT / VID[4] ISEN1
1 2
SV_CLK / SVC_VID[3] IRTN2
1 2
SV_DIO / SVD_VID[2] ISEN2
1
VR_HOT# /
2 IRTN3
VRHOT_ICRIT#
ENABLE ISEN3
SMB_ALERT# IRTN4
SMB_DIO ISEN4
SMB_CLK IRTN5
1
SV_ADDR_GPO_D
ISEN5
2
/ VID[1]
1
PM_ADDR_GPO_C /
2 IRTN6
PM_ADDR_VID[0]
ISEN6
TSEN2
VAR_GATE IRTN7IR3536/38
Digital Multi-Phase Buck Controller
CHL8326/28
ORDERING INFORMATION
Packing
Package Part Number Programming
Qty
IR353M
TR=3000 IR3536MTRPBF
QFN Default
TY=2600 IR3536MTYPBF
P/PBF Lead Free
TR=3000 IR3538MTRPBF
QFN Default
TY=2600 IR3538MTYPBF
TR Tape & Reel / TY - Tray
1
QFN TR=3000 IR3536MxxyyTRP Customer Configuration
yy Configuration File ID
1
QFN TR=3000 IR3538MxxyyTRP Customer Configuration
xx Customer ID
Notes:
Package Type (QFN)
1. Customer Specific Configuration File, where
xx = Customer ID and yy = Configuration File
Part
(Codes assigned by IR Marketing).
6: IR3536
8: IR3538
Package Packing Qty Part Number
T=3000 CHL8326-00CRT
CHL832
QFN
CHL8326-00CRTY
TY=2600
1
QFN T=3000 CHL8326-xxCRT
T Tape & Reel / TY - Tray
T=3000 CHL8328-00CRT
QFN
CHL8328-00CRTY
TY=2600
R Package Type (QFN)
1
QFN T=3000 CHL8328-xxCRT
C Operating Temperature,
Commercial
Notes:
xx Configuration File
1. xx indicates a customer specific configuration file.
Part
6: CHL8326
8: CHL8328
56 55 54 53 52 51 50 49 48 47 46 45 44 43
ISEN8 1 42 ISEN7
48 47 46 45 44 43 42 41 40 39 38 37
RCSP 2 41 RCSP_L2
RCSP_L2
RCSP 1 36
3 40 RCSM_L2
RCSM
RCSM 2 35 RCSM_L2
4 39
VCC VCC
1
3 34 VCC
VCC CFP /
5 38
2 VSEN_L2
VFIXEN_PSI
1
CFP /
VSEN_L2
2 4 33
VSEN 6 37 VRTN_L2
VFIXEN_PSI
CHL8328
VSEN 5 32 VRTN_L2 VRTN 7 36 PWM8
56 Pin 8x8 QFN
CHL8326
8 35
VRTN 6 31 PWM6 RRES PWM7
Top View
48 Pin 7x7 QFN
9 34
TSEN PWM6
7 30 PWM5
RRES
Top View
10 33
V18A PWM5
PWM4
TSEN 8 29
1
VR_READY /
11 32 PWM4
2
PWRGD
V18A 9 28 PWM3
1
VR_READY_L2
2 12 31 PWM3
1
/ PWROK
VR_READY /
10 27 PWM2
2
PWRGD
GPO_B 13 30
PWM2
1
VR_READY_L2 57 GND
2 11 26 PWM1
/ PWROK
14 29
VINSEN PWM1
49 GND
VAR_GATE
VINSEN 12 25
15 16 17 18 19 20 21 22 23 24 25 26 27 28
13 14 15 16 17 18 19 20 21 22 23 24
1
Intel/MPoL mode
2
AMD mode
Figure 4: IR3538/CHL8328 Package Top View, Enlarged
Figure 3: IR3536/CHL8326 Package Top View, Enlarged
2 June 21, 2013 | FINAL | V1.09
1 2
GPO_A / CBOUT IRTN1
1 2
PSI / VID[5] ISEN1
1 2
SV_ALERT / VID[4] IRTN2
1 2
SV_CLK / SVC_VID[3] ISEN2
1 2
IRTN3
SV_DIO / SVD_VID[2]
1
VR_HOT# /
2 ISEN3
VRHOT_ICRIT#
ENABLE IRTN4
ISEN4
SMB_ALERT#
SMB_DIO IRTN5
ISEN5
SMB_CLK
1
SV_ADDR_GPO_D
IRTN6
2
/ VID[1]
1
PM_ADDR_GPO_C /
ISEN6
2
PM_ADDR_VID[0]
1 2
GPO_A / CBOUT IRTN8
1 2
PSI(MPoL) / VID[5]
IRTN1
1 2
SV_ALERT / VID[4]
ISEN1
1 2
SV_CLK / SVC_VID[3] IRTN2
1 2
SV_DIO / SVD_VID[2] ISEN2
1
VR_HOT# /
IRTN3
2
VRHOT_ICRIT#
ENABLE ISEN3
SMB_ALERT# IRTN4
SMB_DIO ISEN4
SMB_CLK IRTN5
1
SV_ADDR_GPO_D
ISEN5
2
/ VID[1]
1
PM_ADDR_GPO_C /
IRTN6
2
PM_ADDR_VID[0]
TSEN2 ISEN6
VAR_GATE IRTN7