Serial Configuration (EPCS) Devices Datasheet C51014-5.1 Datasheet This datasheet describes serial configuration (EPCS) devices. Supported Devices Table 1 lists the supported Altera EPCS devices. Table 1. Altera EPCS Devices On-Chip Recommended Memory Size Cascading Device Decompression ISP Support Reprogrammable Operating (bits) Support Support Voltage (V) EPCS1 1,048,576 No Yes No Yes 3.3 EPCS4 4,194,304 No Yes No Yes 3.3 EPCS16 16,777,216 No Yes No Yes 3.3 EPCS64 67,108,864 No Yes No Yes 3.3 EPCS128 134,217,728 No Yes No Yes 3.3 f For more information about programming EPCS devices using the Altera Programming Unit (APU) or Master Programming Unit (MPU), refer to the Altera Programming Hardware Datasheet. f The EPCS device can be re-programmed in system with ByteBlaster II download cable or an external microprocessor using SRunner. For more information, refer to AN418: SRunner: An Embedded Solution for Serial Configuration Device Programming. Features EPCS devices offer the following features: Supports active serial (AS) x1 configuration scheme Easy-to-use four-pin interface Low cost, low pin count, and non-volatile memory Low current during configuration and near-zero standby mode current 2.7-V to 3.6-V operation EPCS1, EPCS4, and EPCS16 devices available in 8-pin small-outline integrated circuit (SOIC) package EPCS64 and EPCS128 devices available in 16-pin SOIC package 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their ISO respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor 9001:2008 products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any 101 Innovation Drive Registered products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use San Jose, CA 95134 of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders www.altera.com for products or services. April 2014 Altera Corporation Feed back Su b scr ibe Page 2 Functional Description Enables the Nios processor to access unused flash memory through AS memory interface Reprogrammable memory with more than 100,000 erase or program cycles Write protection support for memory sectors using status register bits In-system programming (ISP) support with SRunner software driver ISP support with USB-Blaster , EthernetBlaster, or ByteBlaster II download cables Additional programming support with the APU and programming hardware from BP Microsystems, System General, and other vendors By default, the memory array is erased and the bits are set to 1 Functional Description To configure a system using an SRAM-based device, each time you power on the device, you must load the configuration data. The EPCS device is a flash memory device that can store configuration data that you use for FPGA configuration purpose after power on. You can use the EPCS device on all FPGA that support AS x1 configuration scheme. For an 8-pin SOIC package, you can migrate vertically from the EPCS1 device to the EPCS4 or EPCS16 device. For a 16-pin SOIC package, you can migrate vertically from the EPCS64 device to the EPCS128 device. With the new data decompression feature supported, you can determine using which EPCS device to store the configuration data for configuring your FPGA. Example 1 shows how you can calculate the compression ratio to determine which EPCS device is suitable for the FPGA. Example 1. Compression Ratio Calculation EP4SGX530 = 189,000,000 bits EPCS128 = 134,217,728 bits Preliminary data indicates that compression typically reduces the configuration bitstream size by 35% to 55%. Assume worst case that is 35% decompression. 189,000,000 bits x 0.65 = 122,850,000 bits The EPCS128 device is suitable. f For more information about the FPGA decompression feature, refer to the configuration chapter in the appropriate device handbook. Serial Configuration (EPCS) Devices Datasheet April 2014 Altera Corporation