IP-PCIE/SRIOV

Intel Arria 10 Avalon Streaming with SR-IOV IP for PCIe* User Guide Updated for Intel Quartus Prime Design Suite: 20.4 Online Version ID: 683686 Send Feedback Version: 2022.01.11 UG-01161Contents Contents 1. Datasheet....................................................................................................................... 6 1.1. Intel Arria 10 Avalon -ST Interface with SR-IOV for PCI Express* Datasheet ............6 1.1.1. SR-IOV Features .......................................................................................7 1.2. Release Information ..............................................................................................8 1.3. Device Family Support ...........................................................................................9 1.4. Debug Features ....................................................................................................9 1.5. IP Core Verification ............................................................................................. 10 1.5.1. Compatibility Testing Environment .............................................................10 1.6. Performance and Resource Utilization .................................................................... 10 1.7. Recommended Speed Grades for SR-IOV Interface................................................... 11 2. Getting Started with the SR-IOV Design Example ........................................................ 12 2.1. Directory Structure for Intel Arria 10 SR-IOV Design Example ................................... 12 2.2. Design Components for the SR-IOV Design Example ................................................13 2.3. Generating the SR-IOV Design Example.................................................................. 14 2.4. Compiling and Simulating the Design for SR-IOV......................................................14 3. Parameter Settings....................................................................................................... 16 3.1. Parameters ........................................................................................................ 16 3.2. Intel Arria 10 Avalon-ST Settings ......................................................................... 18 3.3. Intel Arria 10 SR-IOV System Settings ..................................................................18 3.4. Base Address Register (BAR) Settings ....................................................................20 3.5. SR-IOV Device Identification Registers ...................................................................21 3.6. Intel Arria 10 Interrupt Capabilities ...................................................................... 22 3.7. Physical Function TLP Processing Hints (TPH) ..........................................................23 3.8. Address Translation Services (ATS).........................................................................23 3.9. PCI Express and PCI Capabilities Parameters .......................................................... 24 3.9.1. PCI Express and PCI Capabilities................................................................24 3.9.2. Error Reporting .......................................................................................25 3.9.3. Link Capabilities ......................................................................................26 3.9.4. Slot Capabilities ......................................................................................26 3.9.5. Power Management .................................................................................27 3.10. PHY Characteristics ........................................................................................... 28 3.11. Example Designs................................................................................................28 4. Physical Layout.............................................................................................................29 4.1. Hard IP Block Placement In Intel Cyclone 10 GX Devices..........................................29 4.2. Hard IP Block Placement In Intel Arria 10 Devices................................................... 30 4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates........................ 33 4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate..................... 35 4.5. PCI Express Gen3 Bank Usage Restrictions..............................................................37 5. Interfaces and Signal Descriptions ..............................................................................38 5.1. Avalon-ST TX Interface ........................................................................................39 5.2. Component-Specific Avalon-ST Interface Signals ..................................................... 40 5.3. Avalon-ST RX Interface ........................................................................................44 5.4. BAR Hit Signals .................................................................................................. 45 5.5. Configuration Status Interface .............................................................................. 46 Intel Arria 10 Avalon Streaming with SR-IOV IP for PCIe* User Guide Send Feedback 2