IS61VPD51236a IS61VPD102418a IS61lPD51236a IS61lPD102418a 512K x 36, 1024K x 18 JUl Y 2008 18Mb SYNCHRONOUS PIPElINED, DOUBlE CYClE DESElECT ST aTIC RaM FEaTURES DESCRIPTION The ISSI IS61LPD/VPD51236A and IS61LPD/VP - Inter nal self-timed wr ite cycle D102418A a r e h i g h - s p e e d , l o w - p o w e r s y n c h r o n o u s Individual Byte Wr ite Control and Global Wr ite static RAMs designed to provide burstable, high-perfor mance memory for communication and networking applications. Clock controlled, registered address, data and The IS61LPD/VPD51236A is organized as 524,288 words control by 36 bits, and the IS61LPD/VPD102418A is organized Burst sequence control using MODE input as 1,048,576 words by 18 bits. Fabr icated with ISSI s a d va n c e d C M O S t e c h n o l o g y, t h e d ev i c e i n t e gra t e s a Three chip enable option for simple depth ex- 2-bit burst counter, high-speed SRAM core, and high- pansion and address pipelining drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by Common data inputs and data outputs a positive-edge-tr iggered single clock input. Auto Power-down dur ing deselect Wr ite cycles are inter nally self-timed and are initiated by the Double cycle deselect r ising edge of the clock input. Wr ite cycles can be one to four bytes wide as controlled by the write control inputs. Snooze MODE for reduced-power standby Separate byte enables allow individual bytes to be written. JTAG Boundar y Scan for PBGA package The byte wr ite operation is perfor med by using the byte wr ite enable (BWE) input combined with one or more individual Power Supply byte write signals (BWx). In addition, Global Wr ite (GW) LPD: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% is available for writing all bytes at one time, regardless of the byte write controls. VPD: Vdd 2.5V + 5%, Vqdd 2.5V + 5% Bursts can be initiated with either ADSP (Address Status JEDEC 100-Pin TQFP and 165-pin PBGA Processor) or ADSC (Address Status Cache Controller) package input pins. Subsequent burst addresses can be gener- Lead-free available ated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Inter- leave burst is achieved when this pin is tied HIGH or left floating. FaST a CCESS TIME Symbol Parameter 250 200 Units tkq Clock Access Time 2.6 3.1 ns tkc Cycle Time 4 5 ns Frequency 250 200 MHz Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. 1-800-379-4774 1 Rev. C 07/08/08IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A BLOCK DIAGRAM MODE A0 Q0 CLK CLK A0 BINARY COUNTER A1 Q1 ADV CE A1 512Kx36 ADSC CLR ADSP 1024Kx18 MEMORY ARRAY 19/20 17/18 19/20 A D Q ADDRESS REGISTER CE CLK 36, 36, or 18 or 18 GW D Q DQd BWE BYTE WRITE BWd REGISTERS (x36) CLK D Q DQc BYTE WRITE BWc REGISTERS (x36) CLK D Q DQb BYTE WRITE BWb REGISTERS (x36/x18) CLK D Q DQa BYTE WRITE BWa REGISTERS (x36/x18) CLK CE 4 36, INPUT OUTPUT or 18 CE2 D Q REGISTERS REGISTERS DQa - DQd CE2 ENABLE OE REGISTER CLK CLK CE CLK D Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. 1-800-379-4774 Rev. C 07/08/08