IS61vPS102436A IS61lPS102436A IS61vPS204818A IS61lPS204818A 1Mb x 36, 2Mb x 18 JUNE 2010 36Mb SYNCHRONOUS PIPElINED, SINglE CYClE DESElECT STATIC RAM DESCRIPTION FEATURES T h e ISSI I S 6 1 L P S / V P S 1 0 2 4 3 6 A a n d I S 6 1 L P S / V P S Inter nal self-timed wr ite cycle 204818A are high-speed, low-power synchronous static Individual Byte Wr ite Control and Global Wr ite RAMs designed to provide burstable, high-perfor mance memory for communication and networking applications. Clock controlled, registered address, data and The IS61LPS/VPS102436A is organized as 1,048,476 control words by 36 bits. The IS61LPS/VPS204818A is organized Burst sequence control using MODE input as 2M-word by 18 bits. Fabr icated with ISSI s advanced CMOS technology, the device integrates a 2-bit burst Three chip enable option for simple depth ex- counter, high-speed SRAM core, and high-dr ive capability pansion and address pipelining outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive- Common data inputs and data outputs edge-tr iggered single clock input. Auto Power-down dur ing deselect Wr ite cycles are inter nally self-timed and are initiated by Single cycle deselect the r ising edge of the clock input. Wr ite cycles can be one to four bytes wide as controlled by the write control Snooze MODE for reduced-power standby inputs. Power Supply Separate byte enables allow individual bytes to be written. The byte wr ite operation is perfor med by using the byte LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% write enable (BWE) input combined with one or more VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5% individual byte write signals (BWx). In addition, Global Wr ite (GW) is available for writing all bytes at one time, JEDEC 100-Pin TQFP and 165-ball PBGA regardless of the byte write controls. packages Bursts can be initiated with either ADSP (Address Status Lead-free available Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be gener- ated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence or- der, Linear burst is achieved when this pin is tied LOW. Inter leave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol Parameter 200 166 Units tkq Clock Access Time 3.1 3.5 ns tkc Cycle Time 5 6 ns Frequency 200 166 MHz Copyright 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. C 05/27/2010IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A BLOCK DIAGRAM MODE A0 Q0 CLK CLK A0 BINARY COUNTER A1 Q1 ADV CE A1 1Mx36 ADSC 2Mx18 CLR ADSP MEMORY ARRAY 20/21 18/19 20/21 A D Q ADDRESS REGISTER CE CLK 36, 36, or 18 or 18 GW D Q DQ(a-h) BWE BYTE WRITE BW(a-h) REGISTERS x18: a,b x36: a-d CLK 36, CE 2/4/8 or 18 INPUT OUTPUT CE2 D Q REGISTERS REGISTERS DQa - DQd CE2 ENABLE OE REGISTER CLK CLK CE CLK D Q ENABLE DELAY POWER REGISTER ZZ DOWN CLK OE 2 Integrated Silicon Solution, Inc. Rev. C 05/27/2010