IS61LF25672A IS61VF25672A IS61LF51236A IS61VF51236A IS61LF102418A IS61VF102418A 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH JULY 2010 STATIC RAM DESCRIPTION FEATURES The ISSI IS61LF/VF25672A, IS61LF/VF51236A and Internal self-timed write cycle IS61LF/VF102418A are high-speed, low-power synchro- Individual Byte Write Control and Global Write nous static RAMs designed to provide burstable, high- performance memory for communication and networking Clock controlled, registered address, data and applications. The IS61LF/VF25672A is organized as control 262,144 words by 72 bits. The IS61LF/VF51236A is orga- Burst sequence control using MODE input nized as 524,288 words by 36 bits. The IS61LF/VF102418A is organized as 1,048,576 words by 18 bits. Fabricated Three chip enable option for simple depth expan- with ISSI s advanced CMOS technology, the device inte- sion and address pipelining grates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic cir- Common data inputs and data outputs cuit. All synchronous inputs pass through registers con- Auto Power-down during deselect trolled by a positive-edge-triggered single clock input. Single cycle deselect Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one Snooze MODE for reduced-power standby to four bytes wide as controlled by the write control inputs. JTAG Boundary Scan for PBGA package Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write Power Supply enable (BWE) input combined with one or more individual LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the VF: VDD 2.5V + 5%, VDDQ 2.5V + 5% byte write controls. JEDEC 100-Pin TQFP, 119-pin PBGA, 209-Ball Bursts can be initiated with either ADSP (Address Status PBGA and 165-pin PBGA packages. Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated Lead-free available internally and controlled by the ADV (burst address ad- vance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol Parameter -6.5 -7.5 Units tKQ Clock Access Time 6.5 7.5 ns tKC Cycle Time 7.5 8.5 ns Frequency 133 117 MHz Copyright 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. K 07/29/2010IS61LF25672A IS61LF51236A IS61LF102418A IS61VF25672A IS61VF51236A IS61VF102418A BLOCK DIAGRAM MODE A0 Q0 CLK CLK A0 BINARY COUNTER A1 Q1 ADV CE A1 256Kx72 ADSC 512Kx36 CLR ADSP 1024Kx18 MEMORY ARRAY 19/20 17/18 19/20 D Q A ADDRESS REGISTER CE CLK 36,18 36,18 or 72 or 72 GW D Q DQ(a-d) BWE BYTE WRITE BW(a-h) REGISTERS x18: a,b x36: a-d CLK x72: a-h 36,18 CE 2/4/8 or 72 INPUT CE2 D Q REGISTERS DQa - DQd CE2 ENABLE OE REGISTER CLK CE CLK POWER ZZ DOWN OE 2 Integrated Silicon Solution, Inc. Rev. K 07/29/2010