Product Information


IS61WV51216EDBLL-8TLI electronic component of ISSI

Memory; SRAM; 512kx16bit; 2.4÷3.6V; 8ns; TSOP44 II; -40÷85°C

Manufacturer: ISSI
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges

Price (USD)

1: USD 13.7579 ea
Line Total: USD 13.7579

209 - Global Stock
Ships to you between
Tue. 17 Oct to Thu. 19 Oct
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
209 - Global Stock

Ships to you between Tue. 17 Oct to Thu. 19 Oct

MOQ : 1
Multiples : 1
1 : USD 13.7579
10 : USD 12.4663
25 : USD 12.1758
100 : USD 10.7244
270 : USD 9.9808
540 : USD 9.8994
1080 : USD 9.8994
2565 : USD 9.8994
5130 : USD 9.8994

75 - Global Stock

Ships to you between Wed. 11 Oct to Tue. 17 Oct

MOQ : 1
Multiples : 1
1 : USD 18.018
3 : USD 17.03

Product Category
Access Time
8 ns
Kind Of Memory
Tsop44 Ii
Type Of Integrated Circuit
Memory Organisation
Operating Voltage
2.4 To 3.6 V
Operating Temperature
- 40 To 85 C
Memory Capacity
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IS61WV51216EDALL IS61/64WV51216EDBLL 512K x 16 HIGH-SPEED ASYNCHRONOUS JULY 2020 CMOS STATIC RAM WITH ECC FEATURES DESCRIPTION High-speed access times: 8, 10, 20 ns The ISSI IS61WV51216EDALL and IS61/64WV51216EDBLL are high-speed, 8M-bit static High-performance, low-power CMOS process RAMs organized as 512K words by 16 bits. It is fabri- Multiple center power and ground pins for greater cated using ISSI s high-performance CMOS technology. noise immunity This highly reliable process coupled with innovative Easy memory expansion with CE and OE options circuit design techniques, yields high-performance and low power consumption devices. CE power-down Fully static operation: no clock or refresh When CE is HIGH (deselected), the device assumes required a standby mode at which the power dissipation can be TTL compatible inputs and outputs reduced down with CMOS input levels. Single Power Supply Vdd = 1.65V to 2.2V (IS61WV51216EDALL) Easy memory expansion is provided by using Chip En- Vdd = 2.4V to 3.6V (IS61/64WV51216EDBLL) able and Output Enable inputs, CE and OE. The active Packages available: LOW Write Enable (WE) controls both writing and read- ing of the memory. A data byte allows Upper Byte (UB) 48-ball miniBGA (6mm x 8mm) and Lower Byte (LB) access. 44-pin TSOP (Type II) Industrial and Automotive Temperature Support The device is packaged in the JEDEC standard 44-pin Lead-free available TSOP Type II and 48-pin Mini BGA (6mm x 8mm). Data control for upper and lower bytes FUNCTIONAL BLOCK DIAGRAM Memory Memory A0-A18 ECC ECC Lower IO Array- Upper IO Array- Decoder 512K 512K Array- Array- x4 x4 512Kx8 512Kx8 8 4 8 4 8 8 12 IO0-7 ECC I/O Data 8 8 12 Column I/O Circuit IO8-15 ECC /CE /OE Control /WE Circuit /UB /LB Copyright 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. B1 07/24/2020IS61WV51216EDALL IS61/64WV51216EDBLL 48-pin mini BGA (6mm x 8mm) 1 2 3 4 5 6 A LB OE A0 A1 A2 NC I/O UB A3 A4 CE I/O B 8 0 I/O I/O A5 A6 I/O I/O C 9 10 1 2 GND A7 I/O11 A17 I/O3 VDD D VDD I/O NC A16 I/O GND 12 4 E I/O A14 I/O 14 I/O A15 5 I/O F 13 6 I/O NC A12 A13 WE I/O G 15 7 A18 A8 A9 A10 A11 NC H PIN DESCRIPTIONS A0-A18 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection Vdd Power GND Ground 2 Integrated Silicon Solution, Inc. Rev. B1 07/24/2020

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory
Integrated Silicon Solution
Integrated Silicon Solution ()
Integrated Silicon Solution (ISSI)
ISSI(Integrated Silicon Solution)
ISSI, Integrated Silicon Solution Inc