Product Information

IS62WV12816DBLL-45TLI

IS62WV12816DBLL-45TLI electronic component of ISSI

Datasheet
SRAM 2Mb 128K x 1645ns Async SRAM

Manufacturer: ISSI
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 4.8137 ea
Line Total: USD 4.81

9 - Global Stock
Ships to you between
Thu. 02 May to Mon. 06 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
9 - Global Stock


Ships to you between Thu. 02 May to Mon. 06 May

MOQ : 1
Multiples : 1
1 : USD 3.3005
10 : USD 3.0245
100 : USD 2.714
270 : USD 2.7025
540 : USD 2.599
1080 : USD 2.5185
2565 : USD 2.3805
5130 : USD 2.323
10125 : USD 2.323

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Memory Size
Organization
Access Time
Supply Voltage - Max
Supply Voltage - Min
Maximum Operating Temperature
Minimum Operating Temperature
Mounting Style
Package / Case
Packaging
Supply Current - Max
Memory Type
Series
Brand
Maximum Operating Current
Factory Pack Quantity :
Cnhts
Hts Code
Mxhts
Product Type
Subcategory
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IS62WV12816DALL/DBLL IS65WV12816DALL/DBLL JUNE2013 128Kx 16LO W VOLTAGE, ULTRALO WPO WERCMOSSTATICRAM FEATURES DESCRIPTION The ISSI IS62/65WV12816DALL/DBLL are high-speed, High-speed access time: 35ns, 45ns, 55ns 2M bit static RAMs organized as 128K words by 16 CMOS low power operation bits. It is fabricated using I S S I s high-performance 36 mW (typical) operating CMOS technology. This highly reliable process coupled 9 W (typical) CMOS standby with innovative circuit design techniques, yields high- TTL compatible interface levels performance and low power consumption devices. Single power supply When CS1 is HIGH (deselected) or when CS2 is LOW 1.8V 10%Vdd (IS62/65WV12816d ALL) (deselected) or when CS1 is LOW, CS2 is HIGH and both 2.5V--3.6VV dd (IS62/65WV12816dBLL) LB and UB are HIGH, the device assumes a standby mode Fully static operation: no clock or refresh at which the power dissipation can be reduced down with CMOS input levels. required Three state outputs Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable Data control for upper and lower bytes (WE) controls both writing and reading of the memory. A Industrial and Autotmovie temperature support data byte allows Upper Byte (UB) and Lower Byte (LB) 2CS Option Available access. Lead-free available The IS62/65WV12816DALL/DBLL are packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44- Pin TSOP (TYPE II). FUNCTIONALBLOCK DIA GRAM 128K x 16 A0-A16 DECODER MEMORY ARRAY VDD GND I/O0-I/O7 I/O Lower Byte COLUMN I/O DATA CIRCUIT I/O8-I/O15 Upper Byte CS2 CS1 CONTROL OE CIRCUIT WE UB LB Copyright 2013 Integrated Silicon Solution, Inc.All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services descr ibedCustomers herein. are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiv Productseness. are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 1 Rev. C 05/29/2013IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL PINCONFIGURA TIONS 48-PinminiBGA(6mmx8mm) 48-PinminiBGA(6mmx8mm) 2CSOption(PackageCodeB2) (PackageCode B) 1 2 3 4 5 6 1 2 3 4 5 6 A LB OE A0 A1 A2 N/C A LB OE A0 A1 A2 CS2 I/O UB A3 A4 CSI I/O I/O UB A3 A4 CS1 I/O B 8 0 B 8 0 I/O I/O A5 A6 I/O I/O I/O I/O A5 A6 I/O I/O 9 10 1 2 9 10 1 2 C C GND I/O NC A7 I/O VDD GND I/O NC A7 I/O VDD D 11 3 D 11 3 VDD I/O NC A16 I/O GND VDD I/O NC A16 I/O GND E 12 4 E 12 4 I/O I/O A14 A15 I/O I/O I/O I/O A14 A15 I/O I/O F 14 13 5 6 F 14 13 5 6 A12 A12 I/O15 NC A13 WE I/O I/O15 NC A13 WE I/O G 7 G 7 NC A8 A9 A10 A11 NC NC A8 A9 A10 A11 NC H H 44-Pinmini TSOP(TypeII) PINDESCRIPTIONS (PackageCode T) A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs CS1, CS2 Chip Enable Input A4 1 44 A5 OE Output Enable Input A3 2 43 A6 A2 3 42 A7 WE Write Enable Input A1 4 41 OE LB Lower-byte Control (I/O0-I/O7) A0 5 40 UB CS1 6 39 LB UB Upper-byte Control (I/O8-I/O15) I/O0 7 38 I/O15 I/O1 8 37 I/O14 NC No Connection I/O2 9 36 I/O13 Vdd Power I/O3 10 35 I/O12 VDD 11 34 GND GND Ground GND 12 33 VDD I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A16 18 27 A8 A15 19 26 A9 A14 20 25 A10 A13 21 24 A11 A12 22 23 NC 2 Integrated Silicon Solution, Inc. www.issi.com Rev. C 05/29/2013

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory
Integrated Silicon Solution
Integrated Silicon Solution ()
Integrated Silicon Solution (ISSI)
INTEGRATED SILICON SOLUTIONS INC
ISSI
ISSI(Integrated Silicon Solution)
ISSI, Integrated Silicon Solution Inc
Lumissil

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