Memory Module Speci cations KVR13LS9S6/2 2GB 1Rx16 256M x 64-Bit PC3L-10600 CL9 204-Pin SODIMM DESCRIPTION SPECIFICATIONS This document describes ValueRAM s 256M x 64-bit (2GB) CL(IDD) 9 cycles DDR3L-1333 CL9 SDRAM (Synchronous DRAM) 1Rx16, Row Cycle Time (tRCmin) 49.125ns (min.) memory module, based on four 256M x 16-bit FBGA compo- Refresh to Active/Refresh 260ns (min.) nents. The SPD is programmed to JEDEC standard latency Command Time (tRFCmin) DDR3-1333 timing of 9-9-9 at 1.35V or 1.5V. This 204-pin Row Active Time (tRASmin) 36ns (min.) SODIMM uses gold contact fingers. The electrical and me- Maximum Operating Power (1.35V) 0.945 W* chanical specifications are as follows: UL Rating 94 V - 0 o o Operating Temperature 0 C to 85 C o o Storage Temperature -55 C to +100 C FEATURES *Power will vary depending on the SDRAM used. JEDEC standard 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~ 1.575V) Power Supply VDDQ = 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~ 1.575V) 667MHz fCK for 1333Mb/sec/pin 8 independent internal bank Programmable CAS Latency: 9, 8, 7, 6, 5 Programmable Additive Latency: 0, CL - 2, or CL - 1 clock 8-bit pre-fetch Burst Length: 8 (Interleave without any limit, sequential with starting address 000 only), 4 with tCCD = 4 which does not allow seamless read or write either on the fly using A12 or MRS Bi-directional Differential Data Strobe Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm 1%) On Die Termination using ODT pin Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at 85C < TCASE < 95C Asynchronous Reset PCB : Height 1.180 (30.00mm), single sided component Continued >> Document No. VALUERAM1422-001.A00 04/04/14 Page 1MODULE DIMENSIONS: Document No. VALUERAM1422-001.A00 Page 2