Memory Module Speci cations KVR16LR11S4L/8 8GB 1Rx4 1G x 72-Bit PC3L-12800 CL11 Registered w/Parity VLP 240-Pin DIMM DESCRIPTION SPECIFICATIONS This document describes ValueRAM s 1G x 72-bit (8GB) CL(IDD) 11 cycles DDR3L-1600 CL11 SDRAM (Synchronous DRAM), low voltage, Row Cycle Time (tRCmin) 48.125ns (min.) registered w/parity, 1Rx4 ECC, VLP (very low profile) memory Refresh to Active/Refresh 260ns (min.) module, based on eightenn 1G x 4-bit FBGA components. The Command Time (tRFCmin) SPD is programmed to JEDEC standard latency DDR3-1600 Row Active Time (tRASmin) 35ns (min.) timing of 11-11-11 at 1.35V or 1.5V. This 240-pin DIMM uses Maximum Operating Power (1.35V) = 4.311 W* gold contact fingers. The electrical and mechanical specifica- UL Rating 94 V - 0 tions are as follows: o o Operating Temperature 0 C to 85 C o o Storage Temperature -55 C to +100 C FEATURES *Power will vary depending on the SDRAM and JEDEC standard 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~ Register/PLL used. 1.575V) Power Supply VDDQ = 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~ 1.575V) 800MHz fCK for 1600Mb/sec/pin 8 independent internal bank Programmable CAS Latency: 11, 10, 9, 8, 7, 6 Programmable Additive Latency: 0, CL - 2, or CL - 1 clock 8-bit pre-fetch Burst Length: 8 (Interleave without any limit, sequential with starting address 000 only), 4 with tCCD = 4 which does not allow seamless read or write either on the fly using A12 or MRS Bi-directional Differential Data Strobe Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm 1%) On Die Termination using ODT pin On-DIMM thermal sensor (Grade B) Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at 85C < TCASE < 95C Asynchronous Reset PCB : Height 0.740 (18.75mm), double sided component Continued >> Document No. VALUERAM1385-001.B00 10/09/14 Page 1MODULE DIMENSIONS: Document No. VALUERAM1385-001.B00 Page 2