TC58BVG2S0HTAI0
MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2
4 GBIT (512M 8 BIT) CMOS NAND E PROM
DESCRIPTION
The TC58BVG2S0HTAI0 is a single 3.3V 4Gbit (4,429,185,024 bits) NAND Electrically Erasable and
2
Programmable Read-Only Memory (NAND E PROM) organized as (4096 + 128) bytes 64 pages 2048 blocks.
The device has a 4224- byte static register which allows program and read data to be transferred between the register
and the memory cell array in 4224-bytes increments. The Erase operation is implemented in a single block unit
(256 Kbytes + 8 Kbytes: 4224 bytes 64 pages).
The TC58BVG2S0HTAI0 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
The TC58BVG2S0HTAI0 has ECC logic on the chip and 8bit read errors for each 528Bytes can be corrected
internally.
FEATURES
Organization
x8
Memory cell array 4224 128K 8
Register 4224 8
Page size 4224 bytes
Block size (256K + 8K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Read, Multi Page Program, Multi Block Erase, ECC Status Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 2008 blocks
Max 2048 blocks
Power supply
VCC = 2.7V to 3.6V
Access time
Cell array to register 55 s typ. (Single Page Read) / 90 s typ. (Multi Page Read)
Read Cycle Time 25 ns min (C =50pF)
L
Program/Erase time
Auto Page Program 340 s/page typ.
Auto Block Erase 2.5 ms/block typ.
Operating current
Read (25 ns cycle) 30 mA max
Program (avg.) 30 mA max
Erase (avg.) 30 mA max
Standby 50 A max
Package
TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.)
8bit ECC for each 528Byte is implemented on the chip.
2013-2018 Toshiba Memory Corporation
2018-06-01C
1
TC58BVG2S0HTAI0
PIN ASSIGNMENT (TOP VIEW)
TC58BVG2S0HTAI0
8 8
NC 1 48 NC
NC 2 47 NC
NC 3 46 NC
NC 4 45 NC
NC 5 44 I/O8
NC 6 43 I/O7
7 42 I/O6
8 41 I/O5
9 40 NC
NC 10 39 NC
NC 11 38 NC
VCC 12 37 VCC
VSS 13 36 VSS
NC 14 35 NC
NC 15 34 NC
CLE 16 33 NC
ALE 17 32 I/O4
18 31 I/O3
19 30 I/O2
NC 20 29 I/O1
NC 21 28 NC
NC 22 27 NC
NC 23 26 NC
NC 24 25 NC
PIN NAMES
I/O1 to I/O8 I/O port
CE Chip enable
WE Write enable
RE Read enable
CLE Command latch enable
ALE Address latch enable
WP Write protect
RY/BY Ready/Busy
V Power supply
CC
V Ground
SS
NC No Connection
2013-2018 Toshiba Memory Corporation
2018-06-01C
2